Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1369596	1			T26	1		T27	1		T28	1
all_pins[1]	1369596	1			T26	1		T27	1		T28	1
all_pins[2]	1369596	1			T26	1		T27	1		T28	1
all_pins[3]	1369596	1			T26	1		T27	1		T28	1
all_pins[4]	1369596	1			T26	1		T27	1		T28	1
all_pins[5]	1369596	1			T26	1		T27	1		T28	1
all_pins[6]	1369596	1			T26	1		T27	1		T28	1
all_pins[7]	1369596	1			T26	1		T27	1		T28	1
all_pins[8]	1369596	1			T26	1		T27	1		T28	1
all_pins[9]	1369596	1			T26	1		T27	1		T28	1
all_pins[10]	1369596	1			T26	1		T27	1		T28	1
all_pins[11]	1369596	1			T26	1		T27	1		T28	1
all_pins[12]	1369596	1			T26	1		T27	1		T28	1
all_pins[13]	1369596	1			T26	1		T27	1		T28	1
all_pins[14]	1369596	1			T26	1		T27	1		T28	1
all_pins[15]	1369596	1			T26	1		T27	1		T28	1
all_pins[16]	1369596	1			T26	1		T27	1		T28	1
all_pins[17]	1369596	1			T26	1		T27	1		T28	1
all_pins[18]	1369596	1			T26	1		T27	1		T28	1
all_pins[19]	1369596	1			T26	1		T27	1		T28	1
all_pins[20]	1369596	1			T26	1		T27	1		T28	1
all_pins[21]	1369596	1			T26	1		T27	1		T28	1
all_pins[22]	1369596	1			T26	1		T27	1		T28	1
all_pins[23]	1369596	1			T26	1		T27	1		T28	1
all_pins[24]	1369596	1			T26	1		T27	1		T28	1
all_pins[25]	1369596	1			T26	1		T27	1		T28	1
all_pins[26]	1369596	1			T26	1		T27	1		T28	1
all_pins[27]	1369596	1			T26	1		T27	1		T28	1
all_pins[28]	1369596	1			T26	1		T27	1		T28	1
all_pins[29]	1369596	1			T26	1		T27	1		T28	1
all_pins[30]	1369596	1			T26	1		T27	1		T28	1
all_pins[31]	1369596	1			T26	1		T27	1		T28	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	27249242	1			T26	32		T27	32		T28	32
values[0x1]	16577830	1			T31	1398		T32	467		T33	13870
transitions[0x0=>0x1]	9928940	1			T31	881		T32	242		T33	8214
transitions[0x1=>0x0]	9928794	1			T31	880		T32	241		T33	8214

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	851742	1			T26	1		T27	1		T28	1
all_pins[0]	values[0x1]	517854	1			T31	79		T32	6		T33	441
all_pins[0]	transitions[0x0=>0x1]	321489	1			T31	32		T32	3		T33	311
all_pins[0]	transitions[0x1=>0x0]	319793	1			T31	19		T32	11		T33	195
all_pins[1]	values[0x0]	852265	1			T26	1		T27	1		T28	1
all_pins[1]	values[0x1]	517331	1			T31	33		T32	18		T33	370
all_pins[1]	transitions[0x0=>0x1]	309047	1			T31	12		T32	15		T33	228
all_pins[1]	transitions[0x1=>0x0]	309570	1			T31	58		T32	3		T33	299
all_pins[2]	values[0x0]	854914	1			T26	1		T27	1		T28	1
all_pins[2]	values[0x1]	514682	1			T31	31		T32	14		T33	442
all_pins[2]	transitions[0x0=>0x1]	307372	1			T31	27		T32	5		T33	270
all_pins[2]	transitions[0x1=>0x0]	310021	1			T31	29		T32	9		T33	198
all_pins[3]	values[0x0]	850538	1			T26	1		T27	1		T28	1
all_pins[3]	values[0x1]	519058	1			T31	27		T32	13		T33	403
all_pins[3]	transitions[0x0=>0x1]	312521	1			T31	21		T32	8		T33	232
all_pins[3]	transitions[0x1=>0x0]	308145	1			T31	25		T32	9		T33	271
all_pins[4]	values[0x0]	853855	1			T26	1		T27	1		T28	1
all_pins[4]	values[0x1]	515741	1			T31	39		T32	12		T33	545
all_pins[4]	transitions[0x0=>0x1]	308512	1			T31	27		T32	8		T33	297
all_pins[4]	transitions[0x1=>0x0]	311829	1			T31	15		T32	9		T33	155
all_pins[5]	values[0x0]	850162	1			T26	1		T27	1		T28	1
all_pins[5]	values[0x1]	519434	1			T31	47		T32	5		T33	477
all_pins[5]	transitions[0x0=>0x1]	312256	1			T31	39		T33	217		T34	15
all_pins[5]	transitions[0x1=>0x0]	308563	1			T31	31		T32	7		T33	285
all_pins[6]	values[0x0]	852802	1			T26	1		T27	1		T28	1
all_pins[6]	values[0x1]	516794	1			T31	63		T32	13		T33	346
all_pins[6]	transitions[0x0=>0x1]	308675	1			T31	45		T32	12		T33	176
all_pins[6]	transitions[0x1=>0x0]	311315	1			T31	29		T32	4		T33	307
all_pins[7]	values[0x0]	852544	1			T26	1		T27	1		T28	1
all_pins[7]	values[0x1]	517052	1			T31	19		T32	13		T33	516
all_pins[7]	transitions[0x0=>0x1]	309792	1			T31	8		T32	9		T33	380
all_pins[7]	transitions[0x1=>0x0]	309534	1			T31	52		T32	9		T33	210
all_pins[8]	values[0x0]	850032	1			T26	1		T27	1		T28	1
all_pins[8]	values[0x1]	519564	1			T31	38		T32	13		T33	407
all_pins[8]	transitions[0x0=>0x1]	311033	1			T31	33		T32	7		T33	215
all_pins[8]	transitions[0x1=>0x0]	308521	1			T31	14		T32	7		T33	324
all_pins[9]	values[0x0]	854262	1			T26	1		T27	1		T28	1
all_pins[9]	values[0x1]	515334	1			T31	37		T32	12		T33	373
all_pins[9]	transitions[0x0=>0x1]	308411	1			T31	28		T32	6		T33	256
all_pins[9]	transitions[0x1=>0x0]	312641	1			T31	29		T32	7		T33	290
all_pins[10]	values[0x0]	851132	1			T26	1		T27	1		T28	1
all_pins[10]	values[0x1]	518464	1			T31	50		T32	16		T33	440
all_pins[10]	transitions[0x0=>0x1]	310342	1			T31	23		T32	10		T33	271
all_pins[10]	transitions[0x1=>0x0]	307212	1			T31	10		T32	6		T33	204
all_pins[11]	values[0x0]	853556	1			T26	1		T27	1		T28	1
all_pins[11]	values[0x1]	516040	1			T31	48		T32	12		T33	458
all_pins[11]	transitions[0x0=>0x1]	309547	1			T31	24		T32	5		T33	274
all_pins[11]	transitions[0x1=>0x0]	311971	1			T31	26		T32	9		T33	256
all_pins[12]	values[0x0]	853556	1			T26	1		T27	1		T28	1
all_pins[12]	values[0x1]	516040	1			T31	40		T32	19		T33	434
all_pins[12]	transitions[0x0=>0x1]	309089	1			T31	23		T32	13		T33	236
all_pins[12]	transitions[0x1=>0x0]	309089	1			T31	31		T32	6		T33	260
all_pins[13]	values[0x0]	851433	1			T26	1		T27	1		T28	1
all_pins[13]	values[0x1]	518163	1			T31	26		T32	7		T33	399
all_pins[13]	transitions[0x0=>0x1]	311216	1			T31	15		T32	4		T33	172
all_pins[13]	transitions[0x1=>0x0]	309093	1			T31	29		T32	16		T33	207
all_pins[14]	values[0x0]	853615	1			T26	1		T27	1		T28	1
all_pins[14]	values[0x1]	515981	1			T31	46		T32	15		T33	418
all_pins[14]	transitions[0x0=>0x1]	308421	1			T31	41		T32	11		T33	280
all_pins[14]	transitions[0x1=>0x0]	310603	1			T31	21		T32	3		T33	261
all_pins[15]	values[0x0]	845918	1			T26	1		T27	1		T28	1
all_pins[15]	values[0x1]	523678	1			T31	33		T32	15		T33	456
all_pins[15]	transitions[0x0=>0x1]	314154	1			T31	21		T32	7		T33	267
all_pins[15]	transitions[0x1=>0x0]	306457	1			T31	34		T32	7		T33	229
all_pins[16]	values[0x0]	855165	1			T26	1		T27	1		T28	1
all_pins[16]	values[0x1]	514431	1			T31	65		T32	21		T33	406
all_pins[16]	transitions[0x0=>0x1]	305493	1			T31	51		T32	11		T33	215
all_pins[16]	transitions[0x1=>0x0]	314740	1			T31	19		T32	5		T33	265
all_pins[17]	values[0x0]	851506	1			T26	1		T27	1		T28	1
all_pins[17]	values[0x1]	518090	1			T31	55		T32	19		T33	451
all_pins[17]	transitions[0x0=>0x1]	310971	1			T31	27		T32	4		T33	269
all_pins[17]	transitions[0x1=>0x0]	307312	1			T31	37		T32	6		T33	224
all_pins[18]	values[0x0]	851056	1			T26	1		T27	1		T28	1
all_pins[18]	values[0x1]	518540	1			T31	47		T32	22		T33	370
all_pins[18]	transitions[0x0=>0x1]	310238	1			T31	18		T32	8		T33	198
all_pins[18]	transitions[0x1=>0x0]	309788	1			T31	26		T32	5		T33	279
all_pins[19]	values[0x0]	848131	1			T26	1		T27	1		T28	1
all_pins[19]	values[0x1]	521465	1			T31	52		T32	13		T33	425
all_pins[19]	transitions[0x0=>0x1]	312060	1			T31	40		T32	3		T33	295
all_pins[19]	transitions[0x1=>0x0]	309135	1			T31	35		T32	12		T33	240
all_pins[20]	values[0x0]	850143	1			T26	1		T27	1		T28	1
all_pins[20]	values[0x1]	519453	1			T31	56		T32	21		T33	412
all_pins[20]	transitions[0x0=>0x1]	308914	1			T31	24		T32	10		T33	267
all_pins[20]	transitions[0x1=>0x0]	310926	1			T31	20		T32	2		T33	280
all_pins[21]	values[0x0]	853571	1			T26	1		T27	1		T28	1
all_pins[21]	values[0x1]	516025	1			T31	41		T32	13		T33	407
all_pins[21]	transitions[0x0=>0x1]	308977	1			T31	20		T32	7		T33	264
all_pins[21]	transitions[0x1=>0x0]	312405	1			T31	35		T32	15		T33	269
all_pins[22]	values[0x0]	850792	1			T26	1		T27	1		T28	1
all_pins[22]	values[0x1]	518804	1			T31	37		T32	24		T33	499
all_pins[22]	transitions[0x0=>0x1]	311415	1			T31	24		T32	15		T33	319
all_pins[22]	transitions[0x1=>0x0]	308636	1			T31	28		T32	4		T33	227
all_pins[23]	values[0x0]	852969	1			T26	1		T27	1		T28	1
all_pins[23]	values[0x1]	516627	1			T31	50		T32	20		T33	463
all_pins[23]	transitions[0x0=>0x1]	308786	1			T31	38		T32	4		T33	236
all_pins[23]	transitions[0x1=>0x0]	310963	1			T31	25		T32	8		T33	272
all_pins[24]	values[0x0]	849755	1			T26	1		T27	1		T28	1
all_pins[24]	values[0x1]	519841	1			T31	37		T32	11		T33	489
all_pins[24]	transitions[0x0=>0x1]	310703	1			T31	20		T32	4		T33	296
all_pins[24]	transitions[0x1=>0x0]	307489	1			T31	33		T32	13		T33	270
all_pins[25]	values[0x0]	848478	1			T26	1		T27	1		T28	1
all_pins[25]	values[0x1]	521118	1			T31	36		T32	15		T33	383
all_pins[25]	transitions[0x0=>0x1]	311119	1			T31	23		T32	9		T33	187
all_pins[25]	transitions[0x1=>0x0]	309842	1			T31	24		T32	5		T33	293
all_pins[26]	values[0x0]	850852	1			T26	1		T27	1		T28	1
all_pins[26]	values[0x1]	518744	1			T31	38		T32	13		T33	445
all_pins[26]	transitions[0x0=>0x1]	309596	1			T31	26		T32	9		T33	260
all_pins[26]	transitions[0x1=>0x0]	311970	1			T31	24		T32	11		T33	198
all_pins[27]	values[0x0]	852068	1			T26	1		T27	1		T28	1
all_pins[27]	values[0x1]	517528	1			T31	39		T32	13		T33	471
all_pins[27]	transitions[0x0=>0x1]	309097	1			T31	24		T32	9		T33	230
all_pins[27]	transitions[0x1=>0x0]	310313	1			T31	23		T32	9		T33	204
all_pins[28]	values[0x0]	849391	1			T26	1		T27	1		T28	1
all_pins[28]	values[0x1]	520205	1			T31	41		T32	16		T33	482
all_pins[28]	transitions[0x0=>0x1]	310590	1			T31	30		T32	9		T33	300
all_pins[28]	transitions[0x1=>0x0]	307913	1			T31	28		T32	6		T33	289
all_pins[29]	values[0x0]	849937	1			T26	1		T27	1		T28	1
all_pins[29]	values[0x1]	519659	1			T31	39		T32	14		T33	449
all_pins[29]	transitions[0x0=>0x1]	310215	1			T31	29		T32	8		T33	274
all_pins[29]	transitions[0x1=>0x0]	310761	1			T31	31		T32	10		T33	307
all_pins[30]	values[0x0]	849810	1			T26	1		T27	1		T28	1
all_pins[30]	values[0x1]	519786	1			T31	42		T32	14		T33	468
all_pins[30]	transitions[0x0=>0x1]	311376	1			T31	28		T32	5		T33	287
all_pins[30]	transitions[0x1=>0x0]	311249	1			T31	25		T32	5		T33	268
all_pins[31]	values[0x0]	853292	1			T26	1		T27	1		T28	1
all_pins[31]	values[0x1]	516304	1			T31	67		T32	15		T33	325
all_pins[31]	transitions[0x0=>0x1]	307513	1			T31	40		T32	4		T33	235
all_pins[31]	transitions[0x1=>0x0]	310995	1			T31	15		T32	3		T33	378