Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6002919	1			T26	210		T27	111		T28	144
all_values[1]	6002919	1			T26	210		T27	111		T28	144
all_values[2]	6002919	1			T26	210		T27	111		T28	144
all_values[3]	6002919	1			T26	210		T27	111		T28	144
all_values[4]	6002919	1			T26	210		T27	111		T28	144
all_values[5]	6002919	1			T26	210		T27	111		T28	144
all_values[6]	6002919	1			T26	210		T27	111		T28	144
all_values[7]	6002919	1			T26	210		T27	111		T28	144
all_values[8]	6002919	1			T26	210		T27	111		T28	144
all_values[9]	6002919	1			T26	210		T27	111		T28	144
all_values[10]	6002919	1			T26	210		T27	111		T28	144
all_values[11]	6002919	1			T26	210		T27	111		T28	144
all_values[12]	6002919	1			T26	210		T27	111		T28	144
all_values[13]	6002919	1			T26	210		T27	111		T28	144
all_values[14]	6002919	1			T26	210		T27	111		T28	144
all_values[15]	6002919	1			T26	210		T27	111		T28	144
all_values[16]	6002919	1			T26	210		T27	111		T28	144
all_values[17]	6002919	1			T26	210		T27	111		T28	144
all_values[18]	6002919	1			T26	210		T27	111		T28	144
all_values[19]	6002919	1			T26	210		T27	111		T28	144
all_values[20]	6002919	1			T26	210		T27	111		T28	144
all_values[21]	6002919	1			T26	210		T27	111		T28	144
all_values[22]	6002919	1			T26	210		T27	111		T28	144
all_values[23]	6002919	1			T26	210		T27	111		T28	144
all_values[24]	6002919	1			T26	210		T27	111		T28	144
all_values[25]	6002919	1			T26	210		T27	111		T28	144
all_values[26]	6002919	1			T26	210		T27	111		T28	144
all_values[27]	6002919	1			T26	210		T27	111		T28	144
all_values[28]	6002919	1			T26	210		T27	111		T28	144
all_values[29]	6002919	1			T26	210		T27	111		T28	144
all_values[30]	6002919	1			T26	210		T27	111		T28	144
all_values[31]	6002919	1			T26	210		T27	111		T28	144

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132084028

1

T26

6720

T27

3552

T28

4608

auto[1]

60009380

1

T31

2861

T33

41612

T34

1332

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83907729

1

T26

6720

T27

3552

T28

4608

auto[1]

108185679

1

T31

4833

T33

72477

T34

1758

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

190379398

1

T26

6720

T27

3552

T28

4608

auto[1]

1714010

1

T34

261

T47

2265

T48

306

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2433354	1			T26	210		T27	111		T28	144
all_values[0]	auto[0]	auto[0]	auto[1]	1666915	1			T31	62		T33	1120		T34	29
all_values[0]	auto[0]	auto[1]	auto[0]	188556	1			T31	5		T33	156		T34	21
all_values[0]	auto[0]	auto[1]	auto[1]	1660436	1			T31	113		T33	1187		T34	23
all_values[0]	auto[1]	auto[0]	auto[1]	27007	1			T34	9		T47	33		T48	8
all_values[0]	auto[1]	auto[1]	auto[1]	26651	1			T47	39		T48	2		T111	28
all_values[1]	auto[0]	auto[0]	auto[0]	2432122	1			T26	210		T27	111		T28	144
all_values[1]	auto[0]	auto[0]	auto[1]	1681512	1			T31	96		T33	1100		T34	27
all_values[1]	auto[0]	auto[1]	auto[0]	188525	1			T31	8		T33	213		T34	20
all_values[1]	auto[0]	auto[1]	auto[1]	1647318	1			T31	61		T33	1022		T34	15
all_values[1]	auto[1]	auto[0]	auto[1]	27055	1			T34	5		T47	34		T48	5
all_values[1]	auto[1]	auto[1]	auto[1]	26387	1			T34	2		T47	34		T48	4
all_values[2]	auto[0]	auto[0]	auto[0]	2431827	1			T26	210		T27	111		T28	144
all_values[2]	auto[0]	auto[0]	auto[1]	1680460	1			T31	83		T33	992		T34	15
all_values[2]	auto[0]	auto[1]	auto[0]	189043	1			T31	30		T33	194		T34	22
all_values[2]	auto[0]	auto[1]	auto[1]	1648285	1			T31	61		T33	1183		T34	40
all_values[2]	auto[1]	auto[0]	auto[1]	26675	1			T34	5		T47	42		T48	7
all_values[2]	auto[1]	auto[1]	auto[1]	26629	1			T34	3		T47	37		T48	3
all_values[3]	auto[0]	auto[0]	auto[0]	2432453	1			T26	210		T27	111		T28	144
all_values[3]	auto[0]	auto[0]	auto[1]	1657433	1			T31	118		T33	1074		T34	22
all_values[3]	auto[0]	auto[1]	auto[0]	194842	1			T31	18		T33	195		T34	19
all_values[3]	auto[0]	auto[1]	auto[1]	1664885	1			T31	43		T33	1174		T34	29
all_values[3]	auto[1]	auto[0]	auto[1]	26829	1			T34	6		T47	34		T48	5
all_values[3]	auto[1]	auto[1]	auto[1]	26477	1			T34	3		T47	31		T48	2
all_values[4]	auto[0]	auto[0]	auto[0]	2429901	1			T26	210		T27	111		T28	144
all_values[4]	auto[0]	auto[0]	auto[1]	1668973	1			T31	69		T33	827		T34	15
all_values[4]	auto[0]	auto[1]	auto[0]	189206	1			T31	26		T33	135		T34	20
all_values[4]	auto[0]	auto[1]	auto[1]	1661144	1			T31	68		T33	1486		T34	18
all_values[4]	auto[1]	auto[0]	auto[1]	27047	1			T34	4		T47	29		T48	9
all_values[4]	auto[1]	auto[1]	auto[1]	26648	1			T34	2		T47	41		T48	3
all_values[5]	auto[0]	auto[0]	auto[0]	2431689	1			T26	210		T27	111		T28	144
all_values[5]	auto[0]	auto[0]	auto[1]	1667661	1			T31	98		T33	1111		T34	20
all_values[5]	auto[0]	auto[1]	auto[0]	193449	1			T31	4		T33	128		T34	26
all_values[5]	auto[0]	auto[1]	auto[1]	1656451	1			T31	62		T33	1215		T34	26
all_values[5]	auto[1]	auto[0]	auto[1]	27010	1			T34	6		T47	28		T48	6
all_values[5]	auto[1]	auto[1]	auto[1]	26659	1			T34	4		T47	31		T48	2
all_values[6]	auto[0]	auto[0]	auto[0]	2437347	1			T26	210		T27	111		T28	144
all_values[6]	auto[0]	auto[0]	auto[1]	1664520	1			T31	42		T33	1241		T34	27
all_values[6]	auto[0]	auto[1]	auto[0]	188954	1			T31	24		T33	232		T34	29
all_values[6]	auto[0]	auto[1]	auto[1]	1658314	1			T31	100		T33	891		T34	6
all_values[6]	auto[1]	auto[0]	auto[1]	27248	1			T34	4		T47	30		T48	5
all_values[6]	auto[1]	auto[1]	auto[1]	26536	1			T34	2		T47	42		T48	1
all_values[7]	auto[0]	auto[0]	auto[0]	2430555	1			T26	210		T27	111		T28	144
all_values[7]	auto[0]	auto[0]	auto[1]	1663202	1			T31	86		T33	910		T34	44
all_values[7]	auto[0]	auto[1]	auto[0]	187755	1			T31	40		T33	148		T34	6
all_values[7]	auto[0]	auto[1]	auto[1]	1667732	1			T31	43		T33	1376		T34	14
all_values[7]	auto[1]	auto[0]	auto[1]	26847	1			T34	7		T47	31		T48	10
all_values[7]	auto[1]	auto[1]	auto[1]	26828	1			T34	1		T47	44		T48	1
all_values[8]	auto[0]	auto[0]	auto[0]	2431136	1			T26	210		T27	111		T28	144
all_values[8]	auto[0]	auto[0]	auto[1]	1672297	1			T31	120		T33	1142		T34	29
all_values[8]	auto[0]	auto[1]	auto[0]	186260	1			T31	11		T33	136		T34	20
all_values[8]	auto[0]	auto[1]	auto[1]	1659825	1			T31	50		T33	1130		T34	20
all_values[8]	auto[1]	auto[0]	auto[1]	26707	1			T34	5		T47	26		T48	6
all_values[8]	auto[1]	auto[1]	auto[1]	26694	1			T34	2		T47	39		T48	3
all_values[9]	auto[0]	auto[0]	auto[0]	2435207	1			T26	210		T27	111		T28	144
all_values[9]	auto[0]	auto[0]	auto[1]	1681180	1			T31	80		T33	1271		T34	27
all_values[9]	auto[0]	auto[1]	auto[0]	188720	1			T31	21		T33	124		T34	7
all_values[9]	auto[0]	auto[1]	auto[1]	1644387	1			T31	54		T33	1037		T34	26
all_values[9]	auto[1]	auto[0]	auto[1]	27011	1			T34	7		T47	34		T48	9
all_values[9]	auto[1]	auto[1]	auto[1]	26414	1			T47	45		T48	3		T111	34
all_values[10]	auto[0]	auto[0]	auto[0]	2433665	1			T26	210		T27	111		T28	144
all_values[10]	auto[0]	auto[0]	auto[1]	1674015	1			T31	79		T33	1111		T34	41
all_values[10]	auto[0]	auto[1]	auto[0]	189442	1			T31	15		T33	92		T34	20
all_values[10]	auto[0]	auto[1]	auto[1]	1652396	1			T31	71		T33	1213		T34	7
all_values[10]	auto[1]	auto[0]	auto[1]	26906	1			T34	8		T47	30		T48	3
all_values[10]	auto[1]	auto[1]	auto[1]	26495	1			T34	1		T47	34		T48	5
all_values[11]	auto[0]	auto[0]	auto[0]	2432683	1			T26	210		T27	111		T28	144
all_values[11]	auto[0]	auto[0]	auto[1]	1674687	1			T31	81		T33	1054		T34	37
all_values[11]	auto[0]	auto[1]	auto[0]	187955	1			T31	8		T33	82		T34	8
all_values[11]	auto[0]	auto[1]	auto[1]	1653720	1			T31	80		T33	1171		T34	11
all_values[11]	auto[1]	auto[0]	auto[1]	27058	1			T34	9		T47	30		T48	10
all_values[11]	auto[1]	auto[1]	auto[1]	26816	1			T34	2		T47	52		T48	1
all_values[12]	auto[0]	auto[0]	auto[0]	2430195	1			T26	210		T27	111		T28	144
all_values[12]	auto[0]	auto[0]	auto[1]	1676021	1			T31	84		T33	1055		T34	27
all_values[12]	auto[0]	auto[1]	auto[0]	186192	1			T31	7		T33	185		T34	29
all_values[12]	auto[0]	auto[1]	auto[1]	1657099	1			T31	66		T33	1184		T34	31
all_values[12]	auto[1]	auto[0]	auto[1]	26831	1			T34	5		T47	23		T48	6
all_values[12]	auto[1]	auto[1]	auto[1]	26581	1			T34	3		T47	45		T48	3
all_values[13]	auto[0]	auto[0]	auto[0]	2430085	1			T26	210		T27	111		T28	144
all_values[13]	auto[0]	auto[0]	auto[1]	1681770	1			T31	97		T33	1238		T34	28
all_values[13]	auto[0]	auto[1]	auto[0]	186986	1			T31	29		T33	153		T34	27
all_values[13]	auto[0]	auto[1]	auto[1]	1650613	1			T31	43		T33	1049		T34	25
all_values[13]	auto[1]	auto[0]	auto[1]	26804	1			T34	3		T47	48		T48	6
all_values[13]	auto[1]	auto[1]	auto[1]	26661	1			T34	1		T47	32		T48	2
all_values[14]	auto[0]	auto[0]	auto[0]	2430625	1			T26	210		T27	111		T28	144
all_values[14]	auto[0]	auto[0]	auto[1]	1671990	1			T31	57		T33	1127		T34	41
all_values[14]	auto[0]	auto[1]	auto[0]	187738	1			T31	45		T33	123		T34	10
all_values[14]	auto[0]	auto[1]	auto[1]	1659145	1			T31	73		T33	1132		T34	16
all_values[14]	auto[1]	auto[0]	auto[1]	26977	1			T34	5		T47	32		T48	6
all_values[14]	auto[1]	auto[1]	auto[1]	26444	1			T34	2		T47	40		T48	4
all_values[15]	auto[0]	auto[0]	auto[0]	2431314	1			T26	210		T27	111		T28	144
all_values[15]	auto[0]	auto[0]	auto[1]	1654743	1			T31	110		T33	1112		T34	20
all_values[15]	auto[0]	auto[1]	auto[0]	192926	1			T31	18		T33	131		T34	26
all_values[15]	auto[0]	auto[1]	auto[1]	1670057	1			T31	51		T33	1182		T34	19
all_values[15]	auto[1]	auto[0]	auto[1]	27177	1			T34	4		T47	42		T48	9
all_values[15]	auto[1]	auto[1]	auto[1]	26702	1			T34	5		T47	31		T48	1
all_values[16]	auto[0]	auto[0]	auto[0]	2434924	1			T26	210		T27	111		T28	144
all_values[16]	auto[0]	auto[0]	auto[1]	1670657	1			T31	45		T33	1190		T34	26
all_values[16]	auto[0]	auto[1]	auto[0]	192483	1			T31	29		T33	158		T34	20
all_values[16]	auto[0]	auto[1]	auto[1]	1651304	1			T31	107		T33	1040		T34	27
all_values[16]	auto[1]	auto[0]	auto[1]	26847	1			T34	7		T47	30		T48	8
all_values[16]	auto[1]	auto[1]	auto[1]	26704	1			T34	4		T47	42		T48	3
all_values[17]	auto[0]	auto[0]	auto[0]	2437699	1			T26	210		T27	111		T28	144
all_values[17]	auto[0]	auto[0]	auto[1]	1661359	1			T31	49		T33	1059		T34	31
all_values[17]	auto[0]	auto[1]	auto[0]	189418	1			T31	27		T33	117		T34	20
all_values[17]	auto[0]	auto[1]	auto[1]	1661166	1			T31	98		T33	1201		T34	23
all_values[17]	auto[1]	auto[0]	auto[1]	26782	1			T34	7		T47	37		T48	5
all_values[17]	auto[1]	auto[1]	auto[1]	26495	1			T34	1		T47	29		T48	5
all_values[18]	auto[0]	auto[0]	auto[0]	2431192	1			T26	210		T27	111		T28	144
all_values[18]	auto[0]	auto[0]	auto[1]	1664473	1			T31	71		T33	1347		T34	35
all_values[18]	auto[0]	auto[1]	auto[0]	187375	1			T31	16		T33	85		T34	20
all_values[18]	auto[0]	auto[1]	auto[1]	1666209	1			T31	72		T33	947		T34	9
all_values[18]	auto[1]	auto[0]	auto[1]	27012	1			T34	7		T47	31		T48	11
all_values[18]	auto[1]	auto[1]	auto[1]	26658	1			T34	1		T47	32		T111	26
all_values[19]	auto[0]	auto[0]	auto[0]	2431652	1			T26	210		T27	111		T28	144
all_values[19]	auto[0]	auto[0]	auto[1]	1665456	1			T31	86		T33	1173		T34	25
all_values[19]	auto[0]	auto[1]	auto[0]	192434	1			T31	13		T33	134		T34	23
all_values[19]	auto[0]	auto[1]	auto[1]	1659817	1			T31	77		T33	1158		T34	1
all_values[19]	auto[1]	auto[0]	auto[1]	27086	1			T34	9		T47	26		T48	7
all_values[19]	auto[1]	auto[1]	auto[1]	26474	1			T34	4		T47	39		T48	4
all_values[20]	auto[0]	auto[0]	auto[0]	2433406	1			T26	210		T27	111		T28	144
all_values[20]	auto[0]	auto[0]	auto[1]	1664330	1			T31	89		T33	1094		T34	22
all_values[20]	auto[0]	auto[1]	auto[0]	189855	1			T31	12		T33	251		T34	16
all_values[20]	auto[0]	auto[1]	auto[1]	1661584	1			T31	79		T33	1070		T34	23
all_values[20]	auto[1]	auto[0]	auto[1]	27114	1			T34	8		T47	45		T48	5
all_values[20]	auto[1]	auto[1]	auto[1]	26630	1			T34	1		T47	32		T48	2
all_values[21]	auto[0]	auto[0]	auto[0]	2432187	1			T26	210		T27	111		T28	144
all_values[21]	auto[0]	auto[0]	auto[1]	1661775	1			T31	57		T33	1156		T34	26
all_values[21]	auto[0]	auto[1]	auto[0]	190979	1			T31	41		T33	92		T34	36
all_values[21]	auto[0]	auto[1]	auto[1]	1664632	1			T31	75		T33	1090		T34	18
all_values[21]	auto[1]	auto[0]	auto[1]	26888	1			T34	5		T47	44		T48	6
all_values[21]	auto[1]	auto[1]	auto[1]	26458	1			T34	2		T47	39		T48	2
all_values[22]	auto[0]	auto[0]	auto[0]	2435248	1			T26	210		T27	111		T28	144
all_values[22]	auto[0]	auto[0]	auto[1]	1656979	1			T31	97		T33	911		T34	42
all_values[22]	auto[0]	auto[1]	auto[0]	191288	1			T31	15		T33	124		T34	25
all_values[22]	auto[0]	auto[1]	auto[1]	1665613	1			T31	58		T33	1382		T34	10
all_values[22]	auto[1]	auto[0]	auto[1]	27190	1			T34	4		T47	30		T48	9
all_values[22]	auto[1]	auto[1]	auto[1]	26601	1			T34	1		T47	46		T48	3
all_values[23]	auto[0]	auto[0]	auto[0]	2431779	1			T26	210		T27	111		T28	144
all_values[23]	auto[0]	auto[0]	auto[1]	1669352	1			T31	62		T33	1082		T34	5
all_values[23]	auto[0]	auto[1]	auto[0]	191781	1			T31	36		T33	112		T34	21
all_values[23]	auto[0]	auto[1]	auto[1]	1656676	1			T31	84		T33	1222		T34	27
all_values[23]	auto[1]	auto[0]	auto[1]	27023	1			T34	6		T47	37		T48	8
all_values[23]	auto[1]	auto[1]	auto[1]	26308	1			T34	2		T47	31		T48	1
all_values[24]	auto[0]	auto[0]	auto[0]	2433208	1			T26	210		T27	111		T28	144
all_values[24]	auto[0]	auto[0]	auto[1]	1663512	1			T31	87		T33	1010		T34	16
all_values[24]	auto[0]	auto[1]	auto[0]	191495	1			T31	28		T33	150		T34	15
all_values[24]	auto[0]	auto[1]	auto[1]	1661044	1			T31	66		T33	1285		T34	33
all_values[24]	auto[1]	auto[0]	auto[1]	27071	1			T34	7		T47	33		T48	10
all_values[24]	auto[1]	auto[1]	auto[1]	26589	1			T34	1		T47	41		T48	2
all_values[25]	auto[0]	auto[0]	auto[0]	2432771	1			T26	210		T27	111		T28	144
all_values[25]	auto[0]	auto[0]	auto[1]	1671959	1			T31	97		T33	1281		T34	27
all_values[25]	auto[0]	auto[1]	auto[0]	184391	1			T31	18		T33	108		T34	32
all_values[25]	auto[0]	auto[1]	auto[1]	1660126	1			T31	53		T33	1040		T34	13
all_values[25]	auto[1]	auto[0]	auto[1]	27023	1			T34	4		T47	35		T48	5
all_values[25]	auto[1]	auto[1]	auto[1]	26649	1			T34	3		T47	27		T48	3
all_values[26]	auto[0]	auto[0]	auto[0]	2430960	1			T26	210		T27	111		T28	144
all_values[26]	auto[0]	auto[0]	auto[1]	1665612	1			T31	121		T33	1050		T34	30
all_values[26]	auto[0]	auto[1]	auto[0]	188298	1			T33	159		T34	16		T47	146
all_values[26]	auto[0]	auto[1]	auto[1]	1664239	1			T31	59		T33	1219		T34	25
all_values[26]	auto[1]	auto[0]	auto[1]	27262	1			T34	6		T47	43		T48	6
all_values[26]	auto[1]	auto[1]	auto[1]	26548	1			T34	2		T47	28		T48	2
all_values[27]	auto[0]	auto[0]	auto[0]	2431239	1			T26	210		T27	111		T28	144
all_values[27]	auto[0]	auto[0]	auto[1]	1675361	1			T31	89		T33	1109		T34	35
all_values[27]	auto[0]	auto[1]	auto[0]	186794	1			T31	21		T33	131		T34	17
all_values[27]	auto[0]	auto[1]	auto[1]	1655857	1			T31	58		T33	1164		T34	10
all_values[27]	auto[1]	auto[0]	auto[1]	27167	1			T34	5		T47	29		T48	9
all_values[27]	auto[1]	auto[1]	auto[1]	26501	1			T34	4		T47	37		T48	2
all_values[28]	auto[0]	auto[0]	auto[0]	2429273	1			T26	210		T27	111		T28	144
all_values[28]	auto[0]	auto[0]	auto[1]	1666013	1			T31	81		T33	939		T34	30
all_values[28]	auto[0]	auto[1]	auto[0]	189682	1			T31	18		T33	144		T34	25
all_values[28]	auto[0]	auto[1]	auto[1]	1664454	1			T31	58		T33	1383		T34	6
all_values[28]	auto[1]	auto[0]	auto[1]	26918	1			T34	6		T47	48		T48	5
all_values[28]	auto[1]	auto[1]	auto[1]	26579	1			T34	3		T47	27		T48	3
all_values[29]	auto[0]	auto[0]	auto[0]	2432362	1			T26	210		T27	111		T28	144
all_values[29]	auto[0]	auto[0]	auto[1]	1668234	1			T31	90		T33	1125		T34	32
all_values[29]	auto[0]	auto[1]	auto[0]	190619	1			T31	22		T33	128		T34	19
all_values[29]	auto[0]	auto[1]	auto[1]	1658202	1			T31	59		T33	1160		T34	20
all_values[29]	auto[1]	auto[0]	auto[1]	26927	1			T34	5		T47	41		T48	7
all_values[29]	auto[1]	auto[1]	auto[1]	26575	1			T34	5		T47	23		T48	4
all_values[30]	auto[0]	auto[0]	auto[0]	2433218	1			T26	210		T27	111		T28	144
all_values[30]	auto[0]	auto[0]	auto[1]	1654467	1			T31	79		T33	1113		T34	45
all_values[30]	auto[0]	auto[1]	auto[0]	192358	1			T31	20		T33	103		T34	24
all_values[30]	auto[0]	auto[1]	auto[1]	1669010	1			T31	68		T33	1229		T34	6
all_values[30]	auto[1]	auto[0]	auto[1]	27198	1			T34	7		T47	35		T48	9
all_values[30]	auto[1]	auto[1]	auto[1]	26668	1			T34	2		T47	39		T48	2
all_values[31]	auto[0]	auto[0]	auto[0]	2433483	1			T26	210		T27	111		T28	144
all_values[31]	auto[0]	auto[0]	auto[1]	1664706	1			T31	54		T33	1285		T34	29
all_values[31]	auto[0]	auto[1]	auto[0]	193171	1			T31	19		T33	121		T34	30
all_values[31]	auto[0]	auto[1]	auto[1]	1658305	1			T31	107		T33	846		T34	15
all_values[31]	auto[1]	auto[0]	auto[1]	26948	1			T34	5		T47	42		T48	7
all_values[31]	auto[1]	auto[1]	auto[1]	26306	1			T34	2		T47	24		T48	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal