Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[1]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[2]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[3]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[4]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[5]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[6]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[7]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[8]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[9]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[10]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[11]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[12]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[13]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[14]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[15]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[16]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[17]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[18]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[19]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[20]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[21]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[22]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[23]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[24]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[25]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[26]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[27]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[28]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[29]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[30]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[31]	5974530	1			T26	398		T27	225		T28	186

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102010116

1

T26

3286

T27

1473

T28

3713

auto[1]

89174844

1

T26

9450

T27

5727

T28

2239

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160274212

1

T26

6803

T27

5280

T28

4725

auto[1]

30910748

1

T26

5933

T27

1920

T28

1227

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151504073

1

T26

6616

T27

3734

T28

4545

auto[1]

39680887

1

T26

6120

T27

3466

T28

1407

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2221591	1			T26	9		T27	3		T28	69
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2022795	1			T26	110		T27	84		T28	55
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	484221	1			T26	84		T27	40		T28	22
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	479818	1			T27	12		T28	10		T29	159
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	282383	1			T26	107		T27	71		T29	13
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	483722	1			T26	88		T27	15		T28	30
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2231701	1			T26	8		T27	10		T28	81
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2017532	1			T26	87		T27	67		T28	52
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	488640	1			T26	100		T27	37		T28	10
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	476251	1			T27	2		T28	25		T29	109
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	278733	1			T26	106		T27	59		T29	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	481673	1			T26	97		T27	50		T28	18
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2219418	1			T26	12		T27	8		T28	68
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2028095	1			T26	93		T27	71		T28	53
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	485134	1			T26	90		T27	37		T28	30
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	477586	1			T27	9		T28	21		T29	116
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	281909	1			T26	89		T27	62		T29	23
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	482388	1			T26	114		T27	38		T28	14
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2240550	1			T26	11		T27	10		T28	63
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2007230	1			T26	89		T27	89		T28	53
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	486031	1			T26	94		T27	36		T28	42
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	477928	1			T27	9		T28	14		T29	219
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	281913	1			T26	98		T27	60		T29	26
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	480878	1			T26	106		T27	21		T28	14
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2219988	1			T26	13		T27	4		T28	81
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2027293	1			T26	90		T27	84		T28	44
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	487496	1			T26	104		T27	38		T28	18
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	476773	1			T27	6		T28	24		T29	123
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	282279	1			T26	102		T27	66		T29	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	480701	1			T26	89		T27	27		T28	19
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2225491	1			T26	14		T27	10		T28	72
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2024164	1			T26	87		T27	101		T28	58
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	485203	1			T26	94		T27	30		T28	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	475291	1			T27	1		T28	16		T29	210
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	282396	1			T26	125		T27	52		T29	26
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	481985	1			T26	78		T27	31		T28	24
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2228376	1			T26	11		T27	11		T28	64
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2015131	1			T26	78		T27	86		T28	55
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	487330	1			T26	94		T27	18		T28	23
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	478797	1			T27	3		T28	26		T29	193
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	282115	1			T26	108		T27	93		T29	20
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	482781	1			T26	107		T27	14		T28	18
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2228962	1			T26	9		T27	6		T28	70
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2016683	1			T26	94		T27	73		T28	50
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	487643	1			T26	108		T27	32		T28	18
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	478775	1			T27	12		T28	34		T29	93
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	281227	1			T26	94		T27	70		T29	10
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	481240	1			T26	93		T27	32		T28	14
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2230649	1			T26	10		T27	6		T28	66
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2018606	1			T26	111		T27	80		T28	51
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	485720	1			T26	78		T27	25		T28	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	475908	1			T27	9		T28	32		T29	86
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	283399	1			T26	97		T27	82		T29	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	480248	1			T26	102		T27	23		T28	27
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2225675	1			T26	13		T27	11		T28	77
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2024538	1			T26	96		T27	83		T28	50
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	486589	1			T26	114		T27	47		T28	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	476065	1			T27	1		T28	26		T29	129
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	280264	1			T26	109		T27	68		T29	24
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	481399	1			T26	66		T27	15		T28	21
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2224182	1			T26	9		T27	11		T28	85
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2023978	1			T26	134		T27	94		T28	46
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	486695	1			T26	84		T27	18		T28	27
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	476459	1			T27	5		T28	18		T29	131
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	279877	1			T26	98		T27	69		T29	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	483339	1			T26	73		T27	28		T28	10
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2219544	1			T26	11		T27	7		T28	66
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2026743	1			T26	90		T27	67		T28	51
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	487091	1			T26	105		T27	25		T28	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	477465	1			T27	6		T28	24		T29	121
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	282000	1			T26	108		T27	70		T29	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	481687	1			T26	84		T27	50		T28	24
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2226346	1			T26	8		T27	12		T28	66
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2021296	1			T26	101		T27	80		T28	47
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	485332	1			T26	94		T27	38		T28	18
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	475192	1			T27	7		T28	29		T29	120
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	283738	1			T26	85		T27	71		T29	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	482626	1			T26	110		T27	17		T28	26
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2222581	1			T26	9		T27	10		T28	85
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2024061	1			T26	119		T27	52		T28	48
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	485840	1			T26	86		T27	31		T28	26
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	478157	1			T27	10		T28	20		T29	93
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	282186	1			T26	110		T27	102		T29	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	481705	1			T26	74		T27	20		T28	7
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2216150	1			T26	12		T27	11		T28	63
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2028130	1			T26	119		T27	48		T28	46
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	486929	1			T26	68		T27	39		T28	10
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	478720	1			T27	8		T28	37		T29	192
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	283250	1			T26	95		T27	91		T29	24
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	481351	1			T26	104		T27	28		T28	30
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2223421	1			T26	12		T27	5		T28	76
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2026849	1			T26	65		T27	68		T28	47
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	486914	1			T26	93		T27	34		T28	31
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	474703	1			T27	11		T28	10		T29	182
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	282031	1			T26	124		T27	61		T29	33
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	480612	1			T26	104		T27	46		T28	22
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2224832	1			T26	11		T27	8		T28	84
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2025676	1			T26	109		T27	91		T28	47
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	482429	1			T26	90		T27	20		T28	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	479523	1			T27	8		T28	11		T29	140
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	283877	1			T26	98		T27	71		T29	14
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	478193	1			T26	90		T27	27		T28	20
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2225104	1			T26	8		T27	8		T28	74
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2028253	1			T26	119		T27	59		T28	51
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	488698	1			T26	83		T27	34		T28	21
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	472757	1			T27	8		T28	16		T29	179
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	280601	1			T26	102		T27	82		T29	28
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	479117	1			T26	86		T27	34		T28	24
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2224180	1			T26	15		T27	3		T28	94
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2026898	1			T26	94		T27	76		T28	53
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	485038	1			T26	86		T27	50		T28	8
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	477926	1			T27	11		T28	18		T29	173
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	281733	1			T26	92		T27	74		T29	28
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	478755	1			T26	111		T27	11		T28	13
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2223322	1			T26	8		T27	4		T28	70
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2029068	1			T26	117		T27	80		T28	46
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	486292	1			T26	90		T27	25		T28	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	476161	1			T27	5		T28	22		T29	203
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	283055	1			T26	92		T27	80		T29	15
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	476632	1			T26	91		T27	31		T28	30
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2226780	1			T26	9		T27	9		T28	78
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2030624	1			T26	136		T27	82		T28	44
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	485003	1			T26	74		T27	39		T28	20
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	475836	1			T27	4		T28	32		T29	156
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	279896	1			T26	97		T27	63		T29	19
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	476391	1			T26	82		T27	28		T28	12
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2229487	1			T26	9		T27	9		T28	72
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2017382	1			T26	119		T27	75		T28	45
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	485248	1			T26	110		T27	40		T28	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	477049	1			T27	5		T28	20		T29	165
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	284740	1			T26	62		T27	60		T29	15
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	480624	1			T26	98		T27	36		T28	35
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2216963	1			T26	9		T27	5		T28	61
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2032269	1			T26	115		T27	61		T28	55
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	483615	1			T26	106		T27	13		T28	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	478163	1			T27	13		T28	30		T29	104
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	283857	1			T26	78		T27	93		T29	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	479663	1			T26	90		T27	40		T28	26
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2224341	1			T26	14		T27	9		T28	76
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2027424	1			T26	74		T27	82		T28	57
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	483883	1			T26	102		T27	19		T28	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	479052	1			T27	6		T28	29		T29	156
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	281739	1			T26	94		T27	98		T29	18
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	478091	1			T26	114		T27	11		T28	18
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2227670	1			T26	7		T27	19		T28	71
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2019382	1			T26	118		T27	113		T28	53
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	483608	1			T26	90		T27	35		T28	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	478912	1			T27	1		T28	26		T29	102
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	284988	1			T26	76		T27	36		T29	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	479970	1			T26	107		T27	21		T28	26
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2220591	1			T26	8		T27	4		T28	81
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2026223	1			T26	97		T27	85		T28	54
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	482793	1			T26	94		T27	21		T28	16
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	481767	1			T27	5		T28	19		T29	115
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	281332	1			T26	100		T27	69		T29	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	481824	1			T26	99		T27	41		T28	16
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2220059	1			T26	10		T27	6		T28	86
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2032221	1			T26	101		T27	98		T28	45
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	482305	1			T26	123		T27	17		T28	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	477171	1			T27	5		T28	23		T29	216
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	282749	1			T26	78		T27	64		T29	35
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	480025	1			T26	86		T27	35		T28	20
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2226350	1			T26	11		T27	2		T28	69
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2019079	1			T26	96		T27	58		T28	50
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	484053	1			T26	83		T27	34		T28	24
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	480893	1			T27	17		T28	26		T29	126
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	283178	1			T26	90		T27	76		T29	16
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	480977	1			T26	118		T27	38		T28	17
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2228608	1			T26	12		T27	8		T28	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2023891	1			T26	117		T27	78		T28	52
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	488386	1			T26	102		T27	10		T28	22
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	476499	1			T27	7		T28	17		T29	131
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	280275	1			T26	92		T27	80		T29	22
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	476871	1			T26	75		T27	42		T28	26
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2218023	1			T26	6		T27	4		T28	69
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2034311	1			T26	113		T27	59		T28	46
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	483353	1			T26	55		T27	30		T28	15
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	478418	1			T27	10		T28	42		T29	176
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	281075	1			T26	150		T27	87		T29	32
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	479350	1			T26	74		T27	35		T28	14
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2225594	1			T26	12		T27	7		T28	72
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2022627	1			T26	119		T27	78		T28	47
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	485005	1			T26	76		T27	49		T28	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	477373	1			T27	9		T28	38		T29	116
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	284540	1			T26	106		T27	69		T29	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	479391	1			T26	85		T27	13		T28	14
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2223816	1			T26	10		T27	6		T28	85
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2026187	1			T26	123		T27	92		T28	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	486572	1			T26	102		T27	33		T28	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	479294	1			T27	8		T28	30		T29	183
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	281211	1			T26	81		T27	58		T29	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	477450	1			T26	82		T27	28		T28	13

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal