Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[1]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[2]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[3]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[4]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[5]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[6]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[7]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[8]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[9]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[10]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[11]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[12]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[13]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[14]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[15]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[16]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[17]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[18]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[19]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[20]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[21]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[22]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[23]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[24]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[25]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[26]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[27]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[28]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[29]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[30]	5974530	1			T26	398		T27	225		T28	186
bins_for_gpio_bits[31]	5974530	1			T26	398		T27	225		T28	186

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102010116

1

T26

3286

T27

1473

T28

3713

auto[1]

89174844

1

T26

9450

T27

5727

T28

2239

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102000786

1

T26

3292

T27

1478

T28

3705

auto[1]

89184174

1

T26

9444

T27

5722

T28

2247

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3098492	1			T26	69		T27	47		T28	96
bins_for_gpio_bits[0]	auto[0]	auto[1]	86839	1			T26	24		T27	8		T28	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	87138	1			T26	24		T27	8		T28	5
bins_for_gpio_bits[0]	auto[1]	auto[1]	2702061	1			T26	281		T27	162		T28	80
bins_for_gpio_bits[1]	auto[0]	auto[0]	3109097	1			T26	88		T27	41		T28	111
bins_for_gpio_bits[1]	auto[0]	auto[1]	87194	1			T26	20		T27	8		T28	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	87495	1			T26	20		T27	8		T28	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	2690744	1			T26	270		T27	168		T28	65
bins_for_gpio_bits[2]	auto[0]	auto[0]	3094895	1			T26	81		T27	48		T28	114
bins_for_gpio_bits[2]	auto[0]	auto[1]	86978	1			T26	21		T27	6		T28	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	87243	1			T26	21		T27	6		T28	5
bins_for_gpio_bits[2]	auto[1]	auto[1]	2705414	1			T26	275		T27	165		T28	62
bins_for_gpio_bits[3]	auto[0]	auto[0]	3117571	1			T26	80		T27	47		T28	115
bins_for_gpio_bits[3]	auto[0]	auto[1]	86652	1			T26	25		T27	8		T28	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	86938	1			T26	25		T27	8		T28	4
bins_for_gpio_bits[3]	auto[1]	auto[1]	2683369	1			T26	268		T27	162		T28	63
bins_for_gpio_bits[4]	auto[0]	auto[0]	3096906	1			T26	92		T27	43		T28	118
bins_for_gpio_bits[4]	auto[0]	auto[1]	87056	1			T26	25		T27	5		T28	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	87351	1			T26	25		T27	5		T28	5
bins_for_gpio_bits[4]	auto[1]	auto[1]	2703217	1			T26	256		T27	172		T28	59
bins_for_gpio_bits[5]	auto[0]	auto[0]	3099256	1			T26	88		T27	35		T28	101
bins_for_gpio_bits[5]	auto[0]	auto[1]	86432	1			T26	20		T27	6		T28	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	86729	1			T26	20		T27	6		T28	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	2702113	1			T26	270		T27	178		T28	79
bins_for_gpio_bits[6]	auto[0]	auto[0]	3106984	1			T26	84		T27	29		T28	108
bins_for_gpio_bits[6]	auto[0]	auto[1]	87210	1			T26	21		T27	3		T28	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	87519	1			T26	21		T27	3		T28	5
bins_for_gpio_bits[6]	auto[1]	auto[1]	2692817	1			T26	272		T27	190		T28	68
bins_for_gpio_bits[7]	auto[0]	auto[0]	3108380	1			T26	91		T27	44		T28	117
bins_for_gpio_bits[7]	auto[0]	auto[1]	86712	1			T26	26		T27	6		T28	5
bins_for_gpio_bits[7]	auto[1]	auto[0]	87000	1			T26	26		T27	6		T28	5
bins_for_gpio_bits[7]	auto[1]	auto[1]	2692438	1			T26	255		T27	169		T28	59
bins_for_gpio_bits[8]	auto[0]	auto[0]	3105587	1			T26	63		T27	36		T28	102
bins_for_gpio_bits[8]	auto[0]	auto[1]	86390	1			T26	25		T27	4		T28	5
bins_for_gpio_bits[8]	auto[1]	auto[0]	86690	1			T26	25		T27	4		T28	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	2695863	1			T26	285		T27	181		T28	73
bins_for_gpio_bits[9]	auto[0]	auto[0]	3101151	1			T26	102		T27	52		T28	107
bins_for_gpio_bits[9]	auto[0]	auto[1]	86895	1			T26	25		T27	8		T28	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	87178	1			T26	25		T27	7		T28	8
bins_for_gpio_bits[9]	auto[1]	auto[1]	2699306	1			T26	246		T27	158		T28	64
bins_for_gpio_bits[10]	auto[0]	auto[0]	3100227	1			T26	68		T27	30		T28	126
bins_for_gpio_bits[10]	auto[0]	auto[1]	86775	1			T26	25		T27	4		T28	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	87109	1			T26	25		T27	4		T28	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	2700419	1			T26	280		T27	187		T28	52
bins_for_gpio_bits[11]	auto[0]	auto[0]	3096918	1			T26	94		T27	33		T28	106
bins_for_gpio_bits[11]	auto[0]	auto[1]	86871	1			T26	23		T27	5		T28	5
bins_for_gpio_bits[11]	auto[1]	auto[0]	87182	1			T26	22		T27	5		T28	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	2703559	1			T26	259		T27	182		T28	70
bins_for_gpio_bits[12]	auto[0]	auto[0]	3099745	1			T26	80		T27	52		T28	106
bins_for_gpio_bits[12]	auto[0]	auto[1]	86849	1			T26	22		T27	6		T28	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	87125	1			T26	22		T27	5		T28	7
bins_for_gpio_bits[12]	auto[1]	auto[1]	2700811	1			T26	274		T27	162		T28	66
bins_for_gpio_bits[13]	auto[0]	auto[0]	3099460	1			T26	75		T27	47		T28	128
bins_for_gpio_bits[13]	auto[0]	auto[1]	86817	1			T26	20		T27	4		T28	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	87118	1			T26	20		T27	4		T28	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	2701135	1			T26	283		T27	170		T28	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	3094581	1			T26	63		T27	52		T28	102
bins_for_gpio_bits[14]	auto[0]	auto[1]	86961	1			T26	17		T27	6		T28	8
bins_for_gpio_bits[14]	auto[1]	auto[0]	87218	1			T26	17		T27	6		T28	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	2705770	1			T26	301		T27	161		T28	68
bins_for_gpio_bits[15]	auto[0]	auto[0]	3098200	1			T26	86		T27	40		T28	112
bins_for_gpio_bits[15]	auto[0]	auto[1]	86546	1			T26	20		T27	10		T28	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	86838	1			T26	19		T27	10		T28	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	2702946	1			T26	273		T27	165		T28	64
bins_for_gpio_bits[16]	auto[0]	auto[0]	3100256	1			T26	78		T27	33		T28	114
bins_for_gpio_bits[16]	auto[0]	auto[1]	86217	1			T26	23		T27	3		T28	5
bins_for_gpio_bits[16]	auto[1]	auto[0]	86528	1			T26	23		T27	3		T28	5
bins_for_gpio_bits[16]	auto[1]	auto[1]	2701529	1			T26	274		T27	186		T28	62
bins_for_gpio_bits[17]	auto[0]	auto[0]	3099526	1			T26	71		T27	46		T28	104
bins_for_gpio_bits[17]	auto[0]	auto[1]	86739	1			T26	21		T27	5		T28	7
bins_for_gpio_bits[17]	auto[1]	auto[0]	87033	1			T26	20		T27	4		T28	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	2701232	1			T26	286		T27	170		T28	68
bins_for_gpio_bits[18]	auto[0]	auto[0]	3100526	1			T26	77		T27	58		T28	115
bins_for_gpio_bits[18]	auto[0]	auto[1]	86333	1			T26	24		T27	6		T28	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	86618	1			T26	24		T27	6		T28	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	2701053	1			T26	273		T27	155		T28	62
bins_for_gpio_bits[19]	auto[0]	auto[0]	3098664	1			T26	73		T27	29		T28	104
bins_for_gpio_bits[19]	auto[0]	auto[1]	86827	1			T26	25		T27	6		T28	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	87111	1			T26	25		T27	5		T28	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	2701928	1			T26	275		T27	185		T28	70
bins_for_gpio_bits[20]	auto[0]	auto[0]	3100777	1			T26	62		T27	44		T28	127
bins_for_gpio_bits[20]	auto[0]	auto[1]	86536	1			T26	21		T27	8		T28	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	86842	1			T26	21		T27	8		T28	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	2700375	1			T26	294		T27	165		T28	53
bins_for_gpio_bits[21]	auto[0]	auto[0]	3104863	1			T26	97		T27	46		T28	99
bins_for_gpio_bits[21]	auto[0]	auto[1]	86631	1			T26	22		T27	8		T28	6
bins_for_gpio_bits[21]	auto[1]	auto[0]	86921	1			T26	22		T27	8		T28	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	2696115	1			T26	257		T27	163		T28	74
bins_for_gpio_bits[22]	auto[0]	auto[0]	3091773	1			T26	87		T27	30		T28	101
bins_for_gpio_bits[22]	auto[0]	auto[1]	86681	1			T26	28		T27	1		T28	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	86968	1			T26	28		T27	1		T28	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	2709108	1			T26	255		T27	193		T28	77
bins_for_gpio_bits[23]	auto[0]	auto[0]	3100375	1			T26	89		T27	32		T28	106
bins_for_gpio_bits[23]	auto[0]	auto[1]	86606	1			T26	27		T27	2		T28	5
bins_for_gpio_bits[23]	auto[1]	auto[0]	86901	1			T26	27		T27	2		T28	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	2700648	1			T26	255		T27	189		T28	70
bins_for_gpio_bits[24]	auto[0]	auto[0]	3103250	1			T26	74		T27	48		T28	102
bins_for_gpio_bits[24]	auto[0]	auto[1]	86657	1			T26	23		T27	7		T28	5
bins_for_gpio_bits[24]	auto[1]	auto[0]	86940	1			T26	23		T27	7		T28	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	2697683	1			T26	278		T27	163		T28	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	3097734	1			T26	74		T27	28		T28	110
bins_for_gpio_bits[25]	auto[0]	auto[1]	87080	1			T26	28		T27	3		T28	6
bins_for_gpio_bits[25]	auto[1]	auto[0]	87417	1			T26	28		T27	2		T28	6
bins_for_gpio_bits[25]	auto[1]	auto[1]	2702299	1			T26	268		T27	192		T28	64
bins_for_gpio_bits[26]	auto[0]	auto[0]	3092819	1			T26	107		T27	23		T28	118
bins_for_gpio_bits[26]	auto[0]	auto[1]	86433	1			T26	27		T27	5		T28	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	86716	1			T26	26		T27	5		T28	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	2708562	1			T26	238		T27	192		T28	62
bins_for_gpio_bits[27]	auto[0]	auto[0]	3104468	1			T26	71		T27	47		T28	113
bins_for_gpio_bits[27]	auto[0]	auto[1]	86556	1			T26	24		T27	6		T28	5
bins_for_gpio_bits[27]	auto[1]	auto[0]	86828	1			T26	23		T27	6		T28	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	2696678	1			T26	280		T27	166		T28	62
bins_for_gpio_bits[28]	auto[0]	auto[0]	3106118	1			T26	89		T27	22		T28	101
bins_for_gpio_bits[28]	auto[0]	auto[1]	87125	1			T26	25		T27	3		T28	7
bins_for_gpio_bits[28]	auto[1]	auto[0]	87375	1			T26	25		T27	3		T28	7
bins_for_gpio_bits[28]	auto[1]	auto[1]	2693912	1			T26	259		T27	197		T28	71
bins_for_gpio_bits[29]	auto[0]	auto[0]	3092636	1			T26	44		T27	40		T28	121
bins_for_gpio_bits[29]	auto[0]	auto[1]	86889	1			T26	18		T27	4		T28	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	87158	1			T26	17		T27	4		T28	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	2707847	1			T26	319		T27	177		T28	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	3100844	1			T26	62		T27	58		T28	120
bins_for_gpio_bits[30]	auto[0]	auto[1]	86885	1			T26	26		T27	7		T28	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	87128	1			T26	26		T27	7		T28	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	2699673	1			T26	284		T27	153		T28	56
bins_for_gpio_bits[31]	auto[0]	auto[0]	3102830	1			T26	87		T27	41		T28	122
bins_for_gpio_bits[31]	auto[0]	auto[1]	86505	1			T26	25		T27	6		T28	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	86852	1			T26	25		T27	6		T28	5
bins_for_gpio_bits[31]	auto[1]	auto[1]	2698343	1			T26	261		T27	172		T28	55