Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4125137 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1877782 |
1 |
|
|
T31 |
126 |
|
T33 |
967 |
|
T34 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5770622 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
232297 |
1 |
|
|
T31 |
7 |
|
T33 |
194 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4145201 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1857718 |
1 |
|
|
T31 |
121 |
|
T33 |
1043 |
|
T34 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
814206 |
1 |
|
|
T31 |
40 |
|
T33 |
476 |
|
T34 |
25 |
| auto[1] |
auto[0] |
auto[1] |
115956 |
1 |
|
|
T31 |
4 |
|
T33 |
109 |
|
T34 |
1 |
| auto[1] |
auto[1] |
auto[0] |
811215 |
1 |
|
|
T31 |
74 |
|
T33 |
373 |
|
T34 |
9 |
| auto[1] |
auto[1] |
auto[1] |
116341 |
1 |
|
|
T31 |
3 |
|
T33 |
85 |
|
T47 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |