Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4129115 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1873804 |
1 |
|
|
T31 |
124 |
|
T33 |
1123 |
|
T34 |
37 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5766440 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
236479 |
1 |
|
|
T31 |
3 |
|
T33 |
260 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4119545 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1883374 |
1 |
|
|
T31 |
91 |
|
T33 |
1463 |
|
T34 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
824136 |
1 |
|
|
T31 |
22 |
|
T33 |
695 |
|
T34 |
22 |
| auto[1] |
auto[0] |
auto[1] |
117952 |
1 |
|
|
T33 |
147 |
|
T47 |
18 |
|
T48 |
3 |
| auto[1] |
auto[1] |
auto[0] |
822759 |
1 |
|
|
T31 |
66 |
|
T33 |
508 |
|
T34 |
21 |
| auto[1] |
auto[1] |
auto[1] |
118527 |
1 |
|
|
T31 |
3 |
|
T33 |
113 |
|
T34 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |