Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4133047 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1869872 |
1 |
|
|
T31 |
73 |
|
T33 |
1369 |
|
T34 |
63 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5122367 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
880552 |
1 |
|
|
T31 |
59 |
|
T33 |
538 |
|
T34 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4124817 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1878102 |
1 |
|
|
T31 |
114 |
|
T33 |
1062 |
|
T34 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
505998 |
1 |
|
|
T31 |
35 |
|
T33 |
226 |
|
T34 |
15 |
| auto[1] |
auto[0] |
auto[1] |
446989 |
1 |
|
|
T31 |
34 |
|
T33 |
199 |
|
T34 |
12 |
| auto[1] |
auto[1] |
auto[0] |
491552 |
1 |
|
|
T31 |
20 |
|
T33 |
298 |
|
T34 |
4 |
| auto[1] |
auto[1] |
auto[1] |
433563 |
1 |
|
|
T31 |
25 |
|
T33 |
339 |
|
T34 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |