Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4113234 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1889685 |
1 |
|
|
T31 |
69 |
|
T33 |
1313 |
|
T34 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5126506 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
876413 |
1 |
|
|
T31 |
42 |
|
T33 |
604 |
|
T34 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4135294 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1867625 |
1 |
|
|
T31 |
103 |
|
T33 |
1259 |
|
T34 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
493285 |
1 |
|
|
T31 |
44 |
|
T33 |
309 |
|
T34 |
6 |
| auto[1] |
auto[0] |
auto[1] |
436196 |
1 |
|
|
T31 |
19 |
|
T33 |
334 |
|
T34 |
13 |
| auto[1] |
auto[1] |
auto[0] |
497927 |
1 |
|
|
T31 |
17 |
|
T33 |
346 |
|
T34 |
14 |
| auto[1] |
auto[1] |
auto[1] |
440217 |
1 |
|
|
T31 |
23 |
|
T33 |
270 |
|
T34 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |