Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4116715 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1886204 |
1 |
|
|
T31 |
61 |
|
T33 |
1369 |
|
T34 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5766379 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
236540 |
1 |
|
|
T31 |
6 |
|
T33 |
269 |
|
T34 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4119216 |
1 |
|
|
T26 |
210 |
|
T27 |
111 |
|
T28 |
144 |
| auto[1] |
1883703 |
1 |
|
|
T31 |
90 |
|
T33 |
1463 |
|
T34 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
821328 |
1 |
|
|
T31 |
64 |
|
T33 |
531 |
|
T34 |
21 |
| auto[1] |
auto[0] |
auto[1] |
117790 |
1 |
|
|
T31 |
4 |
|
T33 |
111 |
|
T47 |
15 |
| auto[1] |
auto[1] |
auto[0] |
825835 |
1 |
|
|
T31 |
20 |
|
T33 |
663 |
|
T34 |
16 |
| auto[1] |
auto[1] |
auto[1] |
118750 |
1 |
|
|
T31 |
2 |
|
T33 |
158 |
|
T34 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |