Unified Coverage Report :: Group Instance : intr_event_lvllow

Group Instance : intr_event_lvllow_pin31

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin31

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin31

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin31

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin4

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin4

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin4

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin4

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin5

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin5

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin5

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin5

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin6

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin6

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin6

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin6

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin7

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin7

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin7

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin7

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin8

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin8

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin8

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin8

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_lvllow_pin9

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_lvllow_pin9

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_lvllow_pin9

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_lvllow_pin9

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin0

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin1

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin10

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin10

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin10

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin10

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin11

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin11

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin11

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin11

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin12

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin12

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin12

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin12

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Group Instance : intr_event_rising_pin13

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance intr_event_rising_pin13

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group Instance intr_event_rising_pin13

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
intr_en	2	0	2	100.00	100	1	1	2
intr_state	2	0	2	100.00	100	1	1	2
type_ctrl_en	2	0	2	100.00	100	1	1	2

Crosses for Group Instance intr_event_rising_pin13

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_type_en_state	4	0	4	100.00	100	1	1	0

Go back
Group Instances:
intr_event_lvllow_pin31
intr_event_lvllow_pin4
intr_event_lvllow_pin5
intr_event_lvllow_pin6
intr_event_lvllow_pin7
intr_event_lvllow_pin8
intr_event_lvllow_pin9
intr_event_rising_pin0
intr_event_rising_pin1
intr_event_rising_pin10
intr_event_rising_pin11
intr_event_rising_pin12
intr_event_rising_pin13

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4125137

T26

210

T27

111

T28

144

auto[1]

1877782

T31

126

T33

967

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5004236

T26

210

T27

111

T28

144

auto[1]

998683

T31

T33

621

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4130766

T26

210

T27

111

T28

144

auto[1]

1872153

T31

T33

1299

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

438322

T31

T33

399

T34

auto[1]

auto[0]

auto[1]

503438

T31

T33

376

T34

auto[1]

auto[0]

435148

T31

T33

279

T34

auto[1]

495245

T31

T33

245

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4125921

T26

210

T27

111

T28

144

auto[1]

1876998

T31

T33

1621

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4996837

T26

210

T27

111

T28

144

auto[1]

1006082

T31

T33

627

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4119991

T26

210

T27

111

T28

144

auto[1]

1882928

T31

T33

1223

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

441798

T31

T33

187

T34

auto[1]

auto[0]

auto[1]

506584

T31

T33

219

T34

auto[1]

auto[0]

435048

T31

T33

409

T34

auto[1]

499498

T31

T33

408

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4126360

T26

210

T27

111

T28

144

auto[1]

1876559

T31

T33

1343

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5010049

T26

210

T27

111

T28

144

auto[1]

992870

T31

T33

797

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4138162

T26

210

T27

111

T28

144

auto[1]

1864757

T31

T33

1576

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

438831

T31

T33

375

T34

auto[1]

auto[0]

auto[1]

499726

T31

T33

357

T34

auto[1]

auto[0]

433056

T31

T33

404

T34

auto[1]

493144

T31

T33

440

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4129115

T26

210

T27

111

T28

144

auto[1]

1873804

T31

124

T33

1123

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5013517

T26

210

T27

111

T28

144

auto[1]

989402

T31

T33

509

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4144434

T26

210

T27

111

T28

144

auto[1]

1858485

T31

108

T33

1015

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

435969

T31

T33

338

T34

auto[1]

auto[0]

auto[1]

495108

T31

T33

346

T34

auto[1]

auto[0]

433114

T31

T33

168

T34

auto[1]

494294

T31

T33

163

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4120604

T26

210

T27

111

T28

144

auto[1]

1882315

T31

T33

1524

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5005271

T26

210

T27

111

T28

144

auto[1]

997648

T31

T33

779

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4134381

T26

210

T27

111

T28

144

auto[1]

1868538

T31

108

T33

1542

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

435586

T31

T33

303

T34

auto[1]

auto[0]

auto[1]

500810

T31

T33

303

T34

auto[1]

auto[0]

435304

T31

T33

460

T47

432

auto[1]

496838

T31

T33

476

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4130140

T26

210

T27

111

T28

144

auto[1]

1872779

T31

T33

1266

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5005870

T26

210

T27

111

T28

144

auto[1]

997049

T31

T33

528

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4133579

T26

210

T27

111

T28

144

auto[1]

1869340

T31

103

T33

1076

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

435536

T31

T33

328

T34

auto[1]

auto[0]

auto[1]

497283

T31

T33

299

T34

auto[1]

auto[0]

436755

T31

T33

220

T47

345

auto[1]

499766

T31

T33

229

T47

102

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4143398

T26

210

T27

111

T28

144

auto[1]

1859521

T31

T33

1161

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5006133

T26

210

T27

111

T28

144

auto[1]

996786

T31

T33

651

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4130662

T26

210

T27

111

T28

144

auto[1]

1872257

T31

118

T33

1373

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

444056

T31

T33

422

T34

auto[1]

auto[0]

auto[1]

507857

T31

T33

377

T34

auto[1]

auto[0]

431415

T31

T33

300

T34

auto[1]

488929

T31

T33

274

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4127276

T26

210

T27

111

T28

144

auto[1]

1875643

T31

118

T33

1343

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5768106

T26

210

T27

111

T28

144

auto[1]

234813

T31

T33

227

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4127062

T26

210

T27

111

T28

144

auto[1]

1875857

T31

T33

1206

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

821245

T31

T33

446

T34

auto[1]

auto[0]

auto[1]

117547

T31

T33

T34

auto[1]

auto[0]

819799

T31

T33

533

T34

auto[1]

117266

T31

T33

129

T47

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4140689

T26

210

T27

111

T28

144

auto[1]

1862230

T31

T33

1235

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5766987

T26

210

T27

111

T28

144

auto[1]

235932

T31

T33

209

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4125851

T26

210

T27

111

T28

144

auto[1]

1877068

T31

103

T33

1141

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

828437

T31

T33

491

T34

auto[1]

auto[0]

auto[1]

119178

T31

T33

110

T34

auto[1]

auto[0]

812699

T31

T33

441

T34

auto[1]

116754

T31

T33

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4134586

T26

210

T27

111

T28

144

auto[1]

1868333

T31

T33

1305

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5767324

T26

210

T27

111

T28

144

auto[1]

235595

T31

T33

192

T47

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4133373

T26

210

T27

111

T28

144

auto[1]

1869546

T31

T33

1074

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

822222

T31

T33

463

T34

auto[1]

auto[0]

auto[1]

118535

T31

T33

T47

auto[1]

auto[0]

811729

T31

T33

419

T34

auto[1]

117060

T31

T33

T47

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4134428

T26

210

T27

111

T28

144

auto[1]

1868491

T31

T33

1253

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5768863

T26

210

T27

111

T28

144

auto[1]

234056

T31

T33

230

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4136476

T26

210

T27

111

T28

144

auto[1]

1866443

T31

T33

1155

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

820715

T31

T33

465

T34

auto[1]

auto[0]

auto[1]

117373

T31

T33

116

T34

auto[1]

auto[0]

811672

T31

T33

460

T34

auto[1]

116683

T33

114

T47

T61

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4133047

T26

210

T27

111

T28

144

auto[1]

1869872

T31

T33

1369

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5768855

T26

210

T27

111

T28

144

auto[1]

234064

T31

T33

212

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4136579

T26

210

T27

111

T28

144

auto[1]

1866340

T31

104

T33

1096

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

814949

T31

T33

400

T34

auto[1]

auto[0]

auto[1]

116981

T31

T33

T47

auto[1]

auto[0]

817327

T31

T33

484

T34

auto[1]

117083

T31

T33

115

T34

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded

Summary for Variable intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4138659

T26

210

T27

111

T28

144

auto[1]

1864260

T31

T33

1202

T34

Summary for Variable intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5769185

T26

210

T27

111

T28

144

auto[1]

233734

T31

T33

213

T34

Summary for Variable type_ctrl_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for type_ctrl_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4135805

T26

210

T27

111

T28

144

auto[1]

1867114

T31

T33

1166

T34

Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	4	0	4	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_type_en_state

Bins

type_ctrl_en

intr_en

intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[1]

auto[0]

827533

T31

T33

460

T34

auto[1]

auto[0]

auto[1]

119174

T31

T33

104

T34

auto[1]

auto[0]

805847

T31

T33

493

T34

auto[1]

114560

T31

T33

109

T47

User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins

NAME	COUNT	STATUS
intr_type_disabled	0	Excluded