Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1512319	1			T33	1		T34	1		T35	1
all_pins[1]	1512319	1			T33	1		T34	1		T35	1
all_pins[2]	1512319	1			T33	1		T34	1		T35	1
all_pins[3]	1512319	1			T33	1		T34	1		T35	1
all_pins[4]	1512319	1			T33	1		T34	1		T35	1
all_pins[5]	1512319	1			T33	1		T34	1		T35	1
all_pins[6]	1512319	1			T33	1		T34	1		T35	1
all_pins[7]	1512319	1			T33	1		T34	1		T35	1
all_pins[8]	1512319	1			T33	1		T34	1		T35	1
all_pins[9]	1512319	1			T33	1		T34	1		T35	1
all_pins[10]	1512319	1			T33	1		T34	1		T35	1
all_pins[11]	1512319	1			T33	1		T34	1		T35	1
all_pins[12]	1512319	1			T33	1		T34	1		T35	1
all_pins[13]	1512319	1			T33	1		T34	1		T35	1
all_pins[14]	1512319	1			T33	1		T34	1		T35	1
all_pins[15]	1512319	1			T33	1		T34	1		T35	1
all_pins[16]	1512319	1			T33	1		T34	1		T35	1
all_pins[17]	1512319	1			T33	1		T34	1		T35	1
all_pins[18]	1512319	1			T33	1		T34	1		T35	1
all_pins[19]	1512319	1			T33	1		T34	1		T35	1
all_pins[20]	1512319	1			T33	1		T34	1		T35	1
all_pins[21]	1512319	1			T33	1		T34	1		T35	1
all_pins[22]	1512319	1			T33	1		T34	1		T35	1
all_pins[23]	1512319	1			T33	1		T34	1		T35	1
all_pins[24]	1512319	1			T33	1		T34	1		T35	1
all_pins[25]	1512319	1			T33	1		T34	1		T35	1
all_pins[26]	1512319	1			T33	1		T34	1		T35	1
all_pins[27]	1512319	1			T33	1		T34	1		T35	1
all_pins[28]	1512319	1			T33	1		T34	1		T35	1
all_pins[29]	1512319	1			T33	1		T34	1		T35	1
all_pins[30]	1512319	1			T33	1		T34	1		T35	1
all_pins[31]	1512319	1			T33	1		T34	1		T35	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30080466	1			T33	32		T34	32		T35	32
values[0x1]	18313742	1			T37	143		T39	1761		T41	3254
transitions[0x0=>0x1]	10967552	1			T37	109		T39	1058		T41	1950
transitions[0x1=>0x0]	10967407	1			T37	109		T39	1057		T41	1950

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	936925	1			T33	1		T34	1		T35	1
all_pins[0]	values[0x1]	575394	1			T37	5		T39	44		T41	171
all_pins[0]	transitions[0x0=>0x1]	356016	1			T37	3		T39	26		T41	141
all_pins[0]	transitions[0x1=>0x0]	352119	1			T37	8		T39	49		T41	32
all_pins[1]	values[0x0]	939234	1			T33	1		T34	1		T35	1
all_pins[1]	values[0x1]	573085	1			T37	9		T39	29		T41	118
all_pins[1]	transitions[0x0=>0x1]	341000	1			T37	6		T39	10		T41	57
all_pins[1]	transitions[0x1=>0x0]	343309	1			T37	2		T39	25		T41	110
all_pins[2]	values[0x0]	938608	1			T33	1		T34	1		T35	1
all_pins[2]	values[0x1]	573711	1			T37	2		T39	58		T41	93
all_pins[2]	transitions[0x0=>0x1]	342901	1			T37	2		T39	45		T41	45
all_pins[2]	transitions[0x1=>0x0]	342275	1			T37	9		T39	16		T41	70
all_pins[3]	values[0x0]	938927	1			T33	1		T34	1		T35	1
all_pins[3]	values[0x1]	573392	1			T37	5		T39	46		T41	105
all_pins[3]	transitions[0x0=>0x1]	341544	1			T37	5		T39	25		T41	67
all_pins[3]	transitions[0x1=>0x0]	341863	1			T37	2		T39	37		T41	55
all_pins[4]	values[0x0]	939771	1			T33	1		T34	1		T35	1
all_pins[4]	values[0x1]	572548	1			T37	4		T39	59		T41	67
all_pins[4]	transitions[0x0=>0x1]	341278	1			T39	35		T41	43		T42	25
all_pins[4]	transitions[0x1=>0x0]	342122	1			T37	1		T39	22		T41	81
all_pins[5]	values[0x0]	938489	1			T33	1		T34	1		T35	1
all_pins[5]	values[0x1]	573830	1			T37	1		T39	77		T41	90
all_pins[5]	transitions[0x0=>0x1]	344162	1			T37	1		T39	45		T41	62
all_pins[5]	transitions[0x1=>0x0]	342880	1			T37	4		T39	27		T41	39
all_pins[6]	values[0x0]	940701	1			T33	1		T34	1		T35	1
all_pins[6]	values[0x1]	571618	1			T37	11		T39	76		T41	131
all_pins[6]	transitions[0x0=>0x1]	342066	1			T37	11		T39	33		T41	69
all_pins[6]	transitions[0x1=>0x0]	344278	1			T37	1		T39	34		T41	28
all_pins[7]	values[0x0]	941022	1			T33	1		T34	1		T35	1
all_pins[7]	values[0x1]	571297	1			T37	6		T39	45		T41	63
all_pins[7]	transitions[0x0=>0x1]	341791	1			T39	23		T41	24		T42	16
all_pins[7]	transitions[0x1=>0x0]	342112	1			T37	5		T39	54		T41	92
all_pins[8]	values[0x0]	938337	1			T33	1		T34	1		T35	1
all_pins[8]	values[0x1]	573982	1			T37	1		T39	46		T41	83
all_pins[8]	transitions[0x0=>0x1]	343992	1			T37	1		T39	32		T41	55
all_pins[8]	transitions[0x1=>0x0]	341307	1			T37	6		T39	31		T41	35
all_pins[9]	values[0x0]	938275	1			T33	1		T34	1		T35	1
all_pins[9]	values[0x1]	574044	1			T37	6		T39	84		T41	84
all_pins[9]	transitions[0x0=>0x1]	343308	1			T37	5		T39	54		T41	67
all_pins[9]	transitions[0x1=>0x0]	343246	1			T39	16		T41	66		T42	25
all_pins[10]	values[0x0]	940124	1			T33	1		T34	1		T35	1
all_pins[10]	values[0x1]	572195	1			T39	54		T41	84		T42	44
all_pins[10]	transitions[0x0=>0x1]	341341	1			T39	13		T41	49		T42	23
all_pins[10]	transitions[0x1=>0x0]	343190	1			T37	6		T39	43		T41	49
all_pins[11]	values[0x0]	938713	1			T33	1		T34	1		T35	1
all_pins[11]	values[0x1]	573606	1			T39	75		T41	143		T42	43
all_pins[11]	transitions[0x0=>0x1]	342928	1			T39	44		T41	98		T42	22
all_pins[11]	transitions[0x1=>0x0]	341517	1			T39	23		T41	39		T42	23
all_pins[12]	values[0x0]	942787	1			T33	1		T34	1		T35	1
all_pins[12]	values[0x1]	569532	1			T37	9		T39	35		T41	113
all_pins[12]	transitions[0x0=>0x1]	340459	1			T37	9		T39	16		T41	61
all_pins[12]	transitions[0x1=>0x0]	344533	1			T39	56		T41	91		T42	24
all_pins[13]	values[0x0]	941161	1			T33	1		T34	1		T35	1
all_pins[13]	values[0x1]	571158	1			T37	1		T39	55		T41	83
all_pins[13]	transitions[0x0=>0x1]	342398	1			T37	1		T39	37		T41	44
all_pins[13]	transitions[0x1=>0x0]	340772	1			T37	9		T39	17		T41	74
all_pins[14]	values[0x0]	939929	1			T33	1		T34	1		T35	1
all_pins[14]	values[0x1]	572390	1			T39	49		T41	86		T42	46
all_pins[14]	transitions[0x0=>0x1]	343262	1			T39	18		T41	58		T42	28
all_pins[14]	transitions[0x1=>0x0]	342030	1			T37	1		T39	24		T41	55
all_pins[15]	values[0x0]	939063	1			T33	1		T34	1		T35	1
all_pins[15]	values[0x1]	573256	1			T37	4		T39	40		T41	128
all_pins[15]	transitions[0x0=>0x1]	343115	1			T37	4		T39	31		T41	82
all_pins[15]	transitions[0x1=>0x0]	342249	1			T39	40		T41	40		T42	24
all_pins[16]	values[0x0]	941540	1			T33	1		T34	1		T35	1
all_pins[16]	values[0x1]	570779	1			T37	13		T39	74		T41	108
all_pins[16]	transitions[0x0=>0x1]	340663	1			T37	10		T39	59		T41	51
all_pins[16]	transitions[0x1=>0x0]	343140	1			T37	1		T39	25		T41	71
all_pins[17]	values[0x0]	939948	1			T33	1		T34	1		T35	1
all_pins[17]	values[0x1]	572371	1			T37	11		T39	72		T41	72
all_pins[17]	transitions[0x0=>0x1]	343460	1			T37	4		T39	27		T41	38
all_pins[17]	transitions[0x1=>0x0]	341868	1			T37	6		T39	29		T41	74
all_pins[18]	values[0x0]	940545	1			T33	1		T34	1		T35	1
all_pins[18]	values[0x1]	571774	1			T39	52		T41	71		T42	41
all_pins[18]	transitions[0x0=>0x1]	342810	1			T39	22		T41	40		T42	18
all_pins[18]	transitions[0x1=>0x0]	343407	1			T37	11		T39	42		T41	41
all_pins[19]	values[0x0]	940074	1			T33	1		T34	1		T35	1
all_pins[19]	values[0x1]	572245	1			T37	11		T39	42		T41	115
all_pins[19]	transitions[0x0=>0x1]	342464	1			T37	11		T39	21		T41	93
all_pins[19]	transitions[0x1=>0x0]	341993	1			T39	31		T41	49		T42	21
all_pins[20]	values[0x0]	944094	1			T33	1		T34	1		T35	1
all_pins[20]	values[0x1]	568225	1			T37	4		T39	49		T41	89
all_pins[20]	transitions[0x0=>0x1]	340681	1			T37	4		T39	25		T41	42
all_pins[20]	transitions[0x1=>0x0]	344701	1			T37	11		T39	18		T41	68
all_pins[21]	values[0x0]	940128	1			T33	1		T34	1		T35	1
all_pins[21]	values[0x1]	572191	1			T37	4		T39	49		T41	125
all_pins[21]	transitions[0x0=>0x1]	343211	1			T37	4		T39	47		T41	75
all_pins[21]	transitions[0x1=>0x0]	339245	1			T37	4		T39	47		T41	39
all_pins[22]	values[0x0]	939584	1			T33	1		T34	1		T35	1
all_pins[22]	values[0x1]	572735	1			T39	51		T41	114		T42	43
all_pins[22]	transitions[0x0=>0x1]	342865	1			T39	47		T41	65		T42	22
all_pins[22]	transitions[0x1=>0x0]	342321	1			T37	4		T39	45		T41	76
all_pins[23]	values[0x0]	944274	1			T33	1		T34	1		T35	1
all_pins[23]	values[0x1]	568045	1			T37	7		T39	59		T41	101
all_pins[23]	transitions[0x0=>0x1]	338982	1			T37	7		T39	36		T41	46
all_pins[23]	transitions[0x1=>0x0]	343672	1			T39	28		T41	59		T42	24
all_pins[24]	values[0x0]	942571	1			T33	1		T34	1		T35	1
all_pins[24]	values[0x1]	569748	1			T37	2		T39	79		T41	102
all_pins[24]	transitions[0x0=>0x1]	342415	1			T39	49		T41	62		T42	28
all_pins[24]	transitions[0x1=>0x0]	340712	1			T37	5		T39	29		T41	61
all_pins[25]	values[0x0]	939549	1			T33	1		T34	1		T35	1
all_pins[25]	values[0x1]	572770	1			T37	1		T39	55		T41	144
all_pins[25]	transitions[0x0=>0x1]	343307	1			T37	1		T39	25		T41	71
all_pins[25]	transitions[0x1=>0x0]	340285	1			T37	2		T39	49		T41	29
all_pins[26]	values[0x0]	939728	1			T33	1		T34	1		T35	1
all_pins[26]	values[0x1]	572591	1			T39	47		T41	100		T42	46
all_pins[26]	transitions[0x0=>0x1]	341923	1			T39	33		T41	37		T42	21
all_pins[26]	transitions[0x1=>0x0]	342102	1			T37	1		T39	41		T41	81
all_pins[27]	values[0x0]	938200	1			T33	1		T34	1		T35	1
all_pins[27]	values[0x1]	574119	1			T37	5		T39	45		T41	95
all_pins[27]	transitions[0x0=>0x1]	343544	1			T37	5		T39	32		T41	58
all_pins[27]	transitions[0x1=>0x0]	342016	1			T39	34		T41	63		T42	21
all_pins[28]	values[0x0]	938610	1			T33	1		T34	1		T35	1
all_pins[28]	values[0x1]	573709	1			T37	4		T39	41		T41	92
all_pins[28]	transitions[0x0=>0x1]	344621	1			T37	1		T39	25		T41	64
all_pins[28]	transitions[0x1=>0x0]	345031	1			T37	2		T39	29		T41	67
all_pins[29]	values[0x0]	940204	1			T33	1		T34	1		T35	1
all_pins[29]	values[0x1]	572115	1			T37	1		T39	53		T41	108
all_pins[29]	transitions[0x0=>0x1]	341040	1			T37	1		T39	37		T41	67
all_pins[29]	transitions[0x1=>0x0]	342634	1			T37	4		T39	25		T41	51
all_pins[30]	values[0x0]	938674	1			T33	1		T34	1		T35	1
all_pins[30]	values[0x1]	573645	1			T37	6		T39	53		T41	114
all_pins[30]	transitions[0x0=>0x1]	342699	1			T37	6		T39	33		T41	77
all_pins[30]	transitions[0x1=>0x0]	341169	1			T37	1		T39	33		T41	71
all_pins[31]	values[0x0]	940677	1			T33	1		T34	1		T35	1
all_pins[31]	values[0x1]	571642	1			T37	10		T39	68		T41	62
all_pins[31]	transitions[0x0=>0x1]	341306	1			T37	7		T39	53		T41	42
all_pins[31]	transitions[0x1=>0x0]	343309	1			T37	3		T39	38		T41	94