Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6231361	1			T33	63		T34	143		T35	308
all_values[1]	6231361	1			T33	63		T34	143		T35	308
all_values[2]	6231361	1			T33	63		T34	143		T35	308
all_values[3]	6231361	1			T33	63		T34	143		T35	308
all_values[4]	6231361	1			T33	63		T34	143		T35	308
all_values[5]	6231361	1			T33	63		T34	143		T35	308
all_values[6]	6231361	1			T33	63		T34	143		T35	308
all_values[7]	6231361	1			T33	63		T34	143		T35	308
all_values[8]	6231361	1			T33	63		T34	143		T35	308
all_values[9]	6231361	1			T33	63		T34	143		T35	308
all_values[10]	6231361	1			T33	63		T34	143		T35	308
all_values[11]	6231361	1			T33	63		T34	143		T35	308
all_values[12]	6231361	1			T33	63		T34	143		T35	308
all_values[13]	6231361	1			T33	63		T34	143		T35	308
all_values[14]	6231361	1			T33	63		T34	143		T35	308
all_values[15]	6231361	1			T33	63		T34	143		T35	308
all_values[16]	6231361	1			T33	63		T34	143		T35	308
all_values[17]	6231361	1			T33	63		T34	143		T35	308
all_values[18]	6231361	1			T33	63		T34	143		T35	308
all_values[19]	6231361	1			T33	63		T34	143		T35	308
all_values[20]	6231361	1			T33	63		T34	143		T35	308
all_values[21]	6231361	1			T33	63		T34	143		T35	308
all_values[22]	6231361	1			T33	63		T34	143		T35	308
all_values[23]	6231361	1			T33	63		T34	143		T35	308
all_values[24]	6231361	1			T33	63		T34	143		T35	308
all_values[25]	6231361	1			T33	63		T34	143		T35	308
all_values[26]	6231361	1			T33	63		T34	143		T35	308
all_values[27]	6231361	1			T33	63		T34	143		T35	308
all_values[28]	6231361	1			T33	63		T34	143		T35	308
all_values[29]	6231361	1			T33	63		T34	143		T35	308
all_values[30]	6231361	1			T33	63		T34	143		T35	308
all_values[31]	6231361	1			T33	63		T34	143		T35	308

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132657229

1

T33

2016

T34

4576

T35

9856

auto[1]

66746323

1

T37

363

T39

4265

T41

12602

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78753898

1

T33

2016

T34

4576

T35

9856

auto[1]

120649654

1

T37

446

T39

7286

T41

22619

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197497475

1

T33

2016

T34

4576

T35

9856

auto[1]

1906077

1

T37

81

T41

846

T43

208

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2250937	1			T33	63		T34	143		T35	308
all_values[0]	auto[0]	auto[0]	auto[1]	1863056	1			T37	7		T39	162		T41	214
all_values[0]	auto[0]	auto[1]	auto[0]	211249	1			T37	2		T39	13		T41	19
all_values[0]	auto[0]	auto[1]	auto[1]	1846522	1			T37	4		T39	72		T41	500
all_values[0]	auto[1]	auto[0]	auto[1]	29706	1			T37	2		T41	5		T43	3
all_values[0]	auto[1]	auto[1]	auto[1]	29891	1			T37	2		T41	24		T43	3
all_values[1]	auto[0]	auto[0]	auto[0]	2253853	1			T33	63		T34	143		T35	308
all_values[1]	auto[0]	auto[0]	auto[1]	1846278	1			T39	105		T41	328		T66	1511
all_values[1]	auto[0]	auto[1]	auto[0]	203808	1			T37	12		T39	43		T41	42
all_values[1]	auto[0]	auto[1]	auto[1]	1867888	1			T37	8		T39	63		T41	370
all_values[1]	auto[1]	auto[0]	auto[1]	30061	1			T41	8		T43	4		T44	28
all_values[1]	auto[1]	auto[1]	auto[1]	29473	1			T37	3		T41	17		T43	3
all_values[2]	auto[0]	auto[0]	auto[0]	2249407	1			T33	63		T34	143		T35	308
all_values[2]	auto[0]	auto[0]	auto[1]	1857733	1			T37	8		T39	122		T41	401
all_values[2]	auto[0]	auto[1]	auto[0]	211822	1			T37	1		T39	18		T41	40
all_values[2]	auto[0]	auto[1]	auto[1]	1852932	1			T37	2		T39	121		T41	279
all_values[2]	auto[1]	auto[0]	auto[1]	29948	1			T37	3		T41	12		T43	6
all_values[2]	auto[1]	auto[1]	auto[1]	29519	1			T41	9		T43	1		T44	29
all_values[3]	auto[0]	auto[0]	auto[0]	2255531	1			T33	63		T34	143		T35	308
all_values[3]	auto[0]	auto[0]	auto[1]	1867257	1			T37	2		T39	98		T41	335
all_values[3]	auto[0]	auto[1]	auto[0]	207984	1			T37	12		T39	23		T41	33
all_values[3]	auto[0]	auto[1]	auto[1]	1840840	1			T37	4		T39	112		T41	364
all_values[3]	auto[1]	auto[0]	auto[1]	30076	1			T37	2		T41	16		T43	4
all_values[3]	auto[1]	auto[1]	auto[1]	29673	1			T37	2		T41	11		T43	3
all_values[4]	auto[0]	auto[0]	auto[0]	2256222	1			T33	63		T34	143		T35	308
all_values[4]	auto[0]	auto[0]	auto[1]	1854010	1			T37	8		T39	98		T41	368
all_values[4]	auto[0]	auto[1]	auto[0]	209882	1			T37	3		T39	29		T41	58
all_values[4]	auto[0]	auto[1]	auto[1]	1851590	1			T37	5		T39	121		T41	318
all_values[4]	auto[1]	auto[0]	auto[1]	29890	1			T37	2		T41	6		T43	9
all_values[4]	auto[1]	auto[1]	auto[1]	29767	1			T41	14		T43	1		T44	26
all_values[5]	auto[0]	auto[0]	auto[0]	2248648	1			T33	63		T34	143		T35	308
all_values[5]	auto[0]	auto[0]	auto[1]	1863901	1			T37	8		T39	102		T41	349
all_values[5]	auto[0]	auto[1]	auto[0]	212283	1			T37	4		T39	12		T41	76
all_values[5]	auto[0]	auto[1]	auto[1]	1847177	1			T39	151		T41	289		T66	1521
all_values[5]	auto[1]	auto[0]	auto[1]	29811	1			T41	14		T43	5		T44	22
all_values[5]	auto[1]	auto[1]	auto[1]	29541	1			T37	1		T41	8		T43	1
all_values[6]	auto[0]	auto[0]	auto[0]	2249623	1			T33	63		T34	143		T35	308
all_values[6]	auto[0]	auto[0]	auto[1]	1861840	1			T37	1		T39	95		T41	272
all_values[6]	auto[0]	auto[1]	auto[0]	207250	1			T37	5		T39	12		T41	73
all_values[6]	auto[0]	auto[1]	auto[1]	1853095	1			T37	11		T39	148		T41	404
all_values[6]	auto[1]	auto[0]	auto[1]	29968	1			T37	1		T41	9		T43	4
all_values[6]	auto[1]	auto[1]	auto[1]	29585	1			T37	2		T41	17		T43	4
all_values[7]	auto[0]	auto[0]	auto[0]	2253698	1			T33	63		T34	143		T35	308
all_values[7]	auto[0]	auto[0]	auto[1]	1861121	1			T39	99		T41	427		T66	1561
all_values[7]	auto[0]	auto[1]	auto[0]	212587	1			T37	15		T39	14		T41	33
all_values[7]	auto[0]	auto[1]	auto[1]	1844415	1			T37	7		T39	103		T41	242
all_values[7]	auto[1]	auto[0]	auto[1]	29891	1			T41	10		T43	7		T44	28
all_values[7]	auto[1]	auto[1]	auto[1]	29649	1			T37	1		T41	9		T43	2
all_values[8]	auto[0]	auto[0]	auto[0]	2255896	1			T33	63		T34	143		T35	308
all_values[8]	auto[0]	auto[0]	auto[1]	1862528	1			T37	13		T39	130		T41	384
all_values[8]	auto[0]	auto[1]	auto[0]	205689	1			T37	12		T39	22		T41	57
all_values[8]	auto[0]	auto[1]	auto[1]	1847644	1			T39	92		T41	302		T66	1482
all_values[8]	auto[1]	auto[0]	auto[1]	30247	1			T41	15		T43	4		T44	35
all_values[8]	auto[1]	auto[1]	auto[1]	29357	1			T37	1		T41	16		T43	1
all_values[9]	auto[0]	auto[0]	auto[0]	2258000	1			T33	63		T34	143		T35	308
all_values[9]	auto[0]	auto[0]	auto[1]	1848543	1			T37	11		T39	62		T41	387
all_values[9]	auto[0]	auto[1]	auto[0]	211106	1			T37	12		T39	17		T41	35
all_values[9]	auto[0]	auto[1]	auto[1]	1853999	1			T37	4		T39	159		T41	294
all_values[9]	auto[1]	auto[0]	auto[1]	29755	1			T41	19		T43	4		T44	19
all_values[9]	auto[1]	auto[1]	auto[1]	29958	1			T37	2		T41	9		T44	27
all_values[10]	auto[0]	auto[0]	auto[0]	2253079	1			T33	63		T34	143		T35	308
all_values[10]	auto[0]	auto[0]	auto[1]	1866391	1			T37	3		T39	95		T41	402
all_values[10]	auto[0]	auto[1]	auto[0]	206671	1			T39	29		T41	25		T66	104
all_values[10]	auto[0]	auto[1]	auto[1]	1845653	1			T39	125		T41	279		T66	1480
all_values[10]	auto[1]	auto[0]	auto[1]	30043	1			T37	3		T41	17		T43	2
all_values[10]	auto[1]	auto[1]	auto[1]	29524	1			T41	13		T43	3		T44	29
all_values[11]	auto[0]	auto[0]	auto[0]	2252748	1			T33	63		T34	143		T35	308
all_values[11]	auto[0]	auto[0]	auto[1]	1856974	1			T37	8		T39	68		T41	272
all_values[11]	auto[0]	auto[1]	auto[0]	208329	1			T37	5		T39	36		T41	18
all_values[11]	auto[0]	auto[1]	auto[1]	1853824	1			T39	158		T41	420		T66	1536
all_values[11]	auto[1]	auto[0]	auto[1]	29964	1			T37	4		T41	11		T43	3
all_values[11]	auto[1]	auto[1]	auto[1]	29522	1			T41	19		T43	6		T44	27
all_values[12]	auto[0]	auto[0]	auto[0]	2253369	1			T33	63		T34	143		T35	308
all_values[12]	auto[0]	auto[0]	auto[1]	1883228	1			T37	5		T39	151		T41	306
all_values[12]	auto[0]	auto[1]	auto[0]	204437	1			T37	6		T39	16		T41	56
all_values[12]	auto[0]	auto[1]	auto[1]	1830561	1			T37	10		T39	73		T41	366
all_values[12]	auto[1]	auto[0]	auto[1]	30118	1			T37	1		T41	4		T43	5
all_values[12]	auto[1]	auto[1]	auto[1]	29648	1			T37	2		T41	20		T43	1
all_values[13]	auto[0]	auto[0]	auto[0]	2254966	1			T33	63		T34	143		T35	308
all_values[13]	auto[0]	auto[0]	auto[1]	1858387	1			T37	10		T39	115		T41	454
all_values[13]	auto[0]	auto[1]	auto[0]	206570	1			T37	4		T39	24		T41	38
all_values[13]	auto[0]	auto[1]	auto[1]	1851841	1			T39	111		T41	248		T66	1418
all_values[13]	auto[1]	auto[0]	auto[1]	30102	1			T37	1		T41	24		T43	4
all_values[13]	auto[1]	auto[1]	auto[1]	29495	1			T37	1		T41	7		T43	2
all_values[14]	auto[0]	auto[0]	auto[0]	2251348	1			T33	63		T34	143		T35	308
all_values[14]	auto[0]	auto[0]	auto[1]	1866123	1			T37	2		T39	96		T41	394
all_values[14]	auto[0]	auto[1]	auto[0]	206972	1			T39	51		T41	44		T66	92
all_values[14]	auto[0]	auto[1]	auto[1]	1847303	1			T39	109		T41	259		T66	1360
all_values[14]	auto[1]	auto[0]	auto[1]	30050	1			T41	18		T43	2		T44	25
all_values[14]	auto[1]	auto[1]	auto[1]	29565	1			T41	11		T43	2		T44	25
all_values[15]	auto[0]	auto[0]	auto[0]	2250770	1			T33	63		T34	143		T35	308
all_values[15]	auto[0]	auto[0]	auto[1]	1857872	1			T37	8		T39	131		T41	236
all_values[15]	auto[0]	auto[1]	auto[0]	213322	1			T37	6		T39	19		T41	86
all_values[15]	auto[0]	auto[1]	auto[1]	1849973	1			T37	2		T39	93		T41	417
all_values[15]	auto[1]	auto[0]	auto[1]	29901	1			T37	2		T41	13		T43	3
all_values[15]	auto[1]	auto[1]	auto[1]	29523	1			T37	3		T41	15		T43	2
all_values[16]	auto[0]	auto[0]	auto[0]	2248184	1			T33	63		T34	143		T35	308
all_values[16]	auto[0]	auto[0]	auto[1]	1882577	1			T37	4		T39	108		T41	348
all_values[16]	auto[0]	auto[1]	auto[0]	207333	1			T37	6		T39	17		T41	29
all_values[16]	auto[0]	auto[1]	auto[1]	1834129	1			T37	14		T39	138		T41	378
all_values[16]	auto[1]	auto[0]	auto[1]	29805	1			T37	1		T41	11		T43	2
all_values[16]	auto[1]	auto[1]	auto[1]	29333	1			T37	3		T41	15		T43	3
all_values[17]	auto[0]	auto[0]	auto[0]	2255219	1			T33	63		T34	143		T35	308
all_values[17]	auto[0]	auto[0]	auto[1]	1861800	1			T37	2		T39	88		T41	363
all_values[17]	auto[0]	auto[1]	auto[0]	205794	1			T37	10		T39	20		T41	36
all_values[17]	auto[0]	auto[1]	auto[1]	1848903	1			T37	9		T39	144		T41	300
all_values[17]	auto[1]	auto[0]	auto[1]	29808	1			T37	2		T41	17		T43	8
all_values[17]	auto[1]	auto[1]	auto[1]	29837	1			T37	2		T41	5		T43	4
all_values[18]	auto[0]	auto[0]	auto[0]	2253408	1			T33	63		T34	143		T35	308
all_values[18]	auto[0]	auto[0]	auto[1]	1864233	1			T37	9		T39	137		T41	402
all_values[18]	auto[0]	auto[1]	auto[0]	207768	1			T37	8		T39	20		T41	47
all_values[18]	auto[0]	auto[1]	auto[1]	1846264	1			T39	104		T41	300		T66	1551
all_values[18]	auto[1]	auto[0]	auto[1]	30065	1			T37	2		T41	15		T43	3
all_values[18]	auto[1]	auto[1]	auto[1]	29623	1			T41	11		T43	2		T44	33
all_values[19]	auto[0]	auto[0]	auto[0]	2248699	1			T33	63		T34	143		T35	308
all_values[19]	auto[0]	auto[0]	auto[1]	1876189	1			T37	2		T39	155		T41	424
all_values[19]	auto[0]	auto[1]	auto[0]	209226	1			T37	5		T39	10		T41	19
all_values[19]	auto[0]	auto[1]	auto[1]	1837734	1			T37	11		T39	86		T41	303
all_values[19]	auto[1]	auto[0]	auto[1]	29991	1			T41	14		T43	3		T44	20
all_values[19]	auto[1]	auto[1]	auto[1]	29522	1			T37	2		T41	14		T43	2
all_values[20]	auto[0]	auto[0]	auto[0]	2256034	1			T33	63		T34	143		T35	308
all_values[20]	auto[0]	auto[0]	auto[1]	1870237	1			T37	9		T39	134		T41	390
all_values[20]	auto[0]	auto[1]	auto[0]	211935	1			T37	4		T39	21		T41	70
all_values[20]	auto[0]	auto[1]	auto[1]	1833911	1			T37	2		T39	96		T41	284
all_values[20]	auto[1]	auto[0]	auto[1]	29805	1			T37	2		T41	18		T43	5
all_values[20]	auto[1]	auto[1]	auto[1]	29439	1			T37	2		T41	9		T43	2
all_values[21]	auto[0]	auto[0]	auto[0]	2250513	1			T33	63		T34	143		T35	308
all_values[21]	auto[0]	auto[0]	auto[1]	1860421	1			T37	9		T39	143		T41	313
all_values[21]	auto[0]	auto[1]	auto[0]	209104	1			T37	2		T39	15		T41	38
all_values[21]	auto[0]	auto[1]	auto[1]	1851742	1			T37	5		T39	89		T41	378
all_values[21]	auto[1]	auto[0]	auto[1]	30237	1			T37	2		T41	16		T43	4
all_values[21]	auto[1]	auto[1]	auto[1]	29344	1			T37	1		T41	13		T43	1
all_values[22]	auto[0]	auto[0]	auto[0]	2251549	1			T33	63		T34	143		T35	308
all_values[22]	auto[0]	auto[0]	auto[1]	1851539	1			T37	14		T39	125		T41	285
all_values[22]	auto[0]	auto[1]	auto[0]	209236	1			T39	15		T41	31		T66	141
all_values[22]	auto[0]	auto[1]	auto[1]	1859486	1			T39	114		T41	402		T66	1562
all_values[22]	auto[1]	auto[0]	auto[1]	29815	1			T37	2		T41	8		T43	2
all_values[22]	auto[1]	auto[1]	auto[1]	29736	1			T41	15		T43	2		T44	23
all_values[23]	auto[0]	auto[0]	auto[0]	2251941	1			T33	63		T34	143		T35	308
all_values[23]	auto[0]	auto[0]	auto[1]	1887827	1			T37	12		T39	125		T41	308
all_values[23]	auto[0]	auto[1]	auto[0]	207133	1			T37	8		T39	11		T41	62
all_values[23]	auto[0]	auto[1]	auto[1]	1824803	1			T37	7		T39	97		T41	353
all_values[23]	auto[1]	auto[0]	auto[1]	30318	1			T37	1		T41	10		T43	4
all_values[23]	auto[1]	auto[1]	auto[1]	29339	1			T41	20		T43	2		T44	28
all_values[24]	auto[0]	auto[0]	auto[0]	2252250	1			T33	63		T34	143		T35	308
all_values[24]	auto[0]	auto[0]	auto[1]	1867931	1			T37	8		T39	69		T41	315
all_values[24]	auto[0]	auto[1]	auto[0]	212495	1			T37	16		T39	19		T41	76
all_values[24]	auto[0]	auto[1]	auto[1]	1838801	1			T37	2		T39	170		T41	327
all_values[24]	auto[1]	auto[0]	auto[1]	30330	1			T37	2		T41	14		T43	5
all_values[24]	auto[1]	auto[1]	auto[1]	29554	1			T41	14		T43	1		T44	23
all_values[25]	auto[0]	auto[0]	auto[0]	2252920	1			T33	63		T34	143		T35	308
all_values[25]	auto[0]	auto[0]	auto[1]	1863216	1			T37	18		T39	130		T41	225
all_values[25]	auto[0]	auto[1]	auto[0]	208458	1			T37	4		T39	1		T41	69
all_values[25]	auto[0]	auto[1]	auto[1]	1847194	1			T39	105		T41	434		T66	1659
all_values[25]	auto[1]	auto[0]	auto[1]	30151	1			T37	2		T41	10		T43	2
all_values[25]	auto[1]	auto[1]	auto[1]	29422	1			T37	1		T41	19		T43	4
all_values[26]	auto[0]	auto[0]	auto[0]	2252181	1			T33	63		T34	143		T35	308
all_values[26]	auto[0]	auto[0]	auto[1]	1868227	1			T37	17		T39	141		T41	376
all_values[26]	auto[0]	auto[1]	auto[0]	213662	1			T37	3		T39	12		T41	36
all_values[26]	auto[0]	auto[1]	auto[1]	1838034	1			T39	98		T41	303		T66	1588
all_values[26]	auto[1]	auto[0]	auto[1]	29712	1			T37	2		T41	17		T43	1
all_values[26]	auto[1]	auto[1]	auto[1]	29545	1			T41	14		T43	4		T44	23
all_values[27]	auto[0]	auto[0]	auto[0]	2248565	1			T33	63		T34	143		T35	308
all_values[27]	auto[0]	auto[0]	auto[1]	1854806	1			T37	7		T39	132		T41	401
all_values[27]	auto[0]	auto[1]	auto[0]	207076	1			T37	2		T39	37		T41	38
all_values[27]	auto[0]	auto[1]	auto[1]	1861303	1			T37	5		T39	81		T41	313
all_values[27]	auto[1]	auto[0]	auto[1]	30032	1			T37	2		T41	14		T43	6
all_values[27]	auto[1]	auto[1]	auto[1]	29579	1			T37	1		T41	10		T43	1
all_values[28]	auto[0]	auto[0]	auto[0]	2254493	1			T33	63		T34	143		T35	308
all_values[28]	auto[0]	auto[0]	auto[1]	1854633	1			T37	6		T39	154		T41	341
all_values[28]	auto[0]	auto[1]	auto[0]	207072	1			T37	2		T39	14		T41	82
all_values[28]	auto[0]	auto[1]	auto[1]	1855520	1			T37	4		T39	75		T41	322
all_values[28]	auto[1]	auto[0]	auto[1]	30096	1			T37	2		T41	14		T43	2
all_values[28]	auto[1]	auto[1]	auto[1]	29547	1			T37	2		T41	12		T43	4
all_values[29]	auto[0]	auto[0]	auto[0]	2251669	1			T33	63		T34	143		T35	308
all_values[29]	auto[0]	auto[0]	auto[1]	1861882	1			T37	9		T39	100		T41	305
all_values[29]	auto[0]	auto[1]	auto[0]	208266	1			T37	12		T39	22		T41	43
all_values[29]	auto[0]	auto[1]	auto[1]	1849803	1			T37	1		T39	125		T41	350
all_values[29]	auto[1]	auto[0]	auto[1]	30326	1			T37	1		T41	10		T43	7
all_values[29]	auto[1]	auto[1]	auto[1]	29415	1			T41	14		T43	3		T44	20
all_values[30]	auto[0]	auto[0]	auto[0]	2250221	1			T33	63		T34	143		T35	308
all_values[30]	auto[0]	auto[0]	auto[1]	1857502	1			T37	10		T39	91		T41	293
all_values[30]	auto[0]	auto[1]	auto[0]	204984	1			T39	26		T41	71		T66	180
all_values[30]	auto[0]	auto[1]	auto[1]	1859246	1			T37	8		T39	136		T41	355
all_values[30]	auto[1]	auto[0]	auto[1]	30081	1			T37	2		T41	11		T43	3
all_values[30]	auto[1]	auto[1]	auto[1]	29327	1			T41	16		T43	5		T44	33
all_values[31]	auto[0]	auto[0]	auto[0]	2249720	1			T33	63		T34	143		T35	308
all_values[31]	auto[0]	auto[0]	auto[1]	1862796	1			T39	104		T41	480		T66	1626
all_values[31]	auto[0]	auto[1]	auto[0]	208734	1			T37	12		T39	6		T41	18
all_values[31]	auto[0]	auto[1]	auto[1]	1850389	1			T37	10		T39	152		T41	222
all_values[31]	auto[1]	auto[0]	auto[1]	30407	1			T41	17		T43	4		T44	24
all_values[31]	auto[1]	auto[1]	auto[1]	29315	1			T37	1		T41	9		T43	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal