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Group Instance : direct_oe_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_oe_cov_obj_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_oe_cov_obj_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_oe_cov_obj_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_oe_cov_obj_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_oe_cov_obj_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_oe_cov_obj_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_oe_cov_obj_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin12
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin12

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin12
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin13
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin13

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin13
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin14
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin14

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin14
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin15
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin15

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin15
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin16
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin16
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin17
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin17

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin17
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin18
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin18

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin18
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin19
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin19

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin19
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin20
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin20

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin20
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin21
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin21

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin21
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin22
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin22

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin22
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin23
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin23

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin23
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin24
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin24

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin24
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin25
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin25

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin25
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin26
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin26

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin26
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin27
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin27

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin27
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : direct_out_cov_obj_pin28
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance direct_out_cov_obj_pin28

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance direct_out_cov_obj_pin28
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
direct_oe_cov_obj_pin4
direct_oe_cov_obj_pin5
direct_oe_cov_obj_pin6
direct_oe_cov_obj_pin7
direct_oe_cov_obj_pin8
direct_oe_cov_obj_pin9
direct_out_cov_obj_pin0
direct_out_cov_obj_pin1
direct_out_cov_obj_pin10
direct_out_cov_obj_pin11
direct_out_cov_obj_pin12
direct_out_cov_obj_pin13
direct_out_cov_obj_pin14
direct_out_cov_obj_pin15
direct_out_cov_obj_pin16
direct_out_cov_obj_pin17
direct_out_cov_obj_pin18
direct_out_cov_obj_pin19
direct_out_cov_obj_pin2
direct_out_cov_obj_pin20
direct_out_cov_obj_pin21
direct_out_cov_obj_pin22
direct_out_cov_obj_pin23
direct_out_cov_obj_pin24
direct_out_cov_obj_pin25
direct_out_cov_obj_pin26
direct_out_cov_obj_pin27
direct_out_cov_obj_pin28

Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89486 1 T33 2 T34 6 T35 15
rising 89485 1 T33 2 T34 6 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 381726 1 T33 20 T34 74 T35 29
auto[1] 153560 1 T33 2 T34 6 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89487 1 T33 2 T34 7 T35 11
rising 89485 1 T33 2 T34 7 T35 11


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 382092 1 T33 19 T34 72 T35 27
auto[1] 153194 1 T33 3 T34 8 T35 28


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89545 1 T33 3 T34 6 T35 15
rising 89541 1 T33 3 T34 6 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 381591 1 T33 18 T34 72 T35 29
auto[1] 153695 1 T33 4 T34 8 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89702 1 T33 2 T34 5 T35 14
rising 89721 1 T33 2 T34 5 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 381644 1 T33 18 T34 75 T35 20
auto[1] 153642 1 T33 4 T34 5 T35 35


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89363 1 T33 2 T34 5 T35 14
rising 89346 1 T33 2 T34 5 T35 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 381522 1 T33 17 T34 75 T35 29
auto[1] 153764 1 T33 5 T34 5 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 89507 1 T34 5 T35 15 T36 34
rising 89515 1 T33 1 T34 5 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 382159 1 T33 21 T34 75 T35 26
auto[1] 153127 1 T33 1 T34 5 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77734 1 T33 1 T34 1 T35 14
rising 77760 1 T33 2 T34 1 T35 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158144 1 T33 3 T34 2 T35 25
auto[1] 153835 1 T33 5 T34 1 T35 30


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77863 1 T33 2 T34 1 T35 16
rising 77874 1 T33 1 T34 1 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158186 1 T33 2 T34 2 T35 26
auto[1] 153793 1 T33 6 T34 1 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77576 1 T33 2 T34 1 T35 15
rising 77599 1 T33 2 T34 1 T35 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158060 1 T33 3 T34 1 T35 26
auto[1] 153919 1 T33 5 T34 2 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77525 1 T33 2 T35 16 T36 35
rising 77545 1 T33 3 T34 1 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158038 1 T33 3 T34 1 T35 27
auto[1] 153941 1 T33 5 T34 2 T35 28


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77482 1 T33 1 T34 1 T35 12
rising 77499 1 T33 1 T35 13 T36 31


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158250 1 T33 5 T34 2 T35 26
auto[1] 153729 1 T33 3 T34 1 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77595 1 T33 2 T35 15 T36 31
rising 77596 1 T33 1 T34 1 T35 14


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157787 1 T33 5 T34 2 T35 25
auto[1] 154192 1 T33 3 T34 1 T35 30


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77590 1 T33 2 T35 14 T36 35
rising 77620 1 T33 2 T34 1 T35 13


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157952 1 T33 4 T34 2 T35 29
auto[1] 154027 1 T33 4 T34 1 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77705 1 T33 3 T34 1 T35 17
rising 77696 1 T33 3 T35 17 T36 33


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158044 1 T33 3 T34 2 T35 31
auto[1] 153935 1 T33 5 T34 1 T35 24


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77681 1 T33 2 T34 1 T35 11
rising 77697 1 T33 2 T35 10 T36 33


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158354 1 T33 5 T34 1 T35 37
auto[1] 153625 1 T33 3 T34 2 T35 18


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77370 1 T33 2 T35 13 T36 36
rising 77406 1 T33 2 T34 1 T35 12


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157811 1 T33 4 T34 2 T35 26
auto[1] 154168 1 T33 4 T34 1 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77652 1 T33 2 T34 1 T35 14
rising 77656 1 T33 1 T34 1 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158035 1 T33 3 T34 1 T35 34
auto[1] 153944 1 T33 5 T34 2 T35 21


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77600 1 T33 2 T34 1 T35 13
rising 77616 1 T33 2 T35 14 T36 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157953 1 T33 5 T34 2 T35 25
auto[1] 154026 1 T33 3 T34 1 T35 30


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77536 1 T33 2 T35 15 T36 32
rising 77551 1 T33 1 T35 15 T36 33


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158331 1 T33 3 T35 30 T36 67
auto[1] 153648 1 T33 5 T34 3 T35 25


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77817 1 T33 2 T34 1 T35 15
rising 77821 1 T33 2 T34 1 T35 15


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158640 1 T33 3 T34 1 T35 34
auto[1] 153339 1 T33 5 T34 2 T35 21


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77584 1 T34 1 T35 16 T36 36
rising 77591 1 T33 1 T35 15 T36 36


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158264 1 T33 6 T34 2 T35 29
auto[1] 153715 1 T33 2 T34 1 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77721 1 T33 2 T35 12 T36 33
rising 77739 1 T33 3 T34 1 T35 13


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158059 1 T33 3 T34 2 T35 28
auto[1] 153920 1 T33 5 T34 1 T35 27


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77537 1 T33 1 T35 16 T36 30
rising 77574 1 T35 15 T36 30 T37 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158213 1 T33 7 T35 29 T36 56
auto[1] 153766 1 T33 1 T34 3 T35 26


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77787 1 T33 1 T35 15 T36 31
rising 77793 1 T33 1 T35 15 T36 31


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157848 1 T33 1 T35 27 T36 70
auto[1] 154131 1 T33 7 T34 3 T35 28


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77645 1 T33 2 T35 17 T36 28
rising 77656 1 T33 1 T35 16 T36 29


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158249 1 T33 5 T34 3 T35 29
auto[1] 153730 1 T33 3 T35 26 T36 79


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77579 1 T33 2 T34 1 T35 14
rising 77570 1 T33 2 T34 1 T35 13


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158034 1 T33 3 T34 2 T35 25
auto[1] 153945 1 T33 5 T34 1 T35 30


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77689 1 T33 2 T34 1 T35 13
rising 77703 1 T33 1 T35 14 T36 32


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158414 1 T33 6 T34 2 T35 26
auto[1] 153565 1 T33 2 T34 1 T35 29


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 77676 1 T33 4 T34 1 T35 12
rising 77703 1 T33 3 T34 1 T35 11


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158074 1 T33 4 T34 2 T35 28
auto[1] 153905 1 T33 4 T34 1 T35 27

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%