Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[1]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[2]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[3]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[4]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[5]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[6]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[7]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[8]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[9]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[10]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[11]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[12]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[13]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[14]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[15]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[16]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[17]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[18]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[19]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[20]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[21]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[22]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[23]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[24]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[25]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[26]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[27]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[28]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[29]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[30]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[31]	6209000	1			T33	123		T34	256		T35	418

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108452233

1

T33

3118

T34

2088

T35

8417

auto[1]

90235767

1

T33

818

T34

6104

T35

4959

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164424488

1

T33

3074

T34

7538

T35

9771

auto[1]

34263512

1

T33

862

T34

654

T35

3605

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

154493552

1

T33

1914

T34

4712

T35

9994

auto[1]

44194448

1

T33

2022

T34

3480

T35

3382

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2288786	1			T33	14		T34	17		T35	161
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	1999842	1			T33	1		T34	45		T35	98
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	538030	1			T33	21		T34	6		T35	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	563300	1			T33	62		T34	32		T35	51
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	283660	1			T33	14		T34	143		T36	118
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	535382	1			T33	11		T34	13		T35	68
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2286723	1			T33	4		T34	43		T35	164
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2000543	1			T34	139		T35	92		T36	140
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	539875	1			T33	2		T34	13		T35	46
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	564225	1			T33	97		T34	7		T35	54
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	283476	1			T33	12		T34	48		T36	145
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	534158	1			T33	8		T34	6		T35	62
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2287277	1			T33	15		T34	17		T35	131
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	1999778	1			T33	2		T34	89		T35	102
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	541272	1			T33	22		T34	5		T35	85
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	560543	1			T33	51		T34	22		T35	32
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	283394	1			T33	10		T34	113		T36	111
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	536736	1			T33	23		T34	10		T35	68
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2288812	1			T33	35		T34	18		T35	122
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	1997894	1			T33	10		T34	38		T35	113
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	541090	1			T34	2		T35	84		T36	130
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	565903	1			T33	58		T34	34		T35	30
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	281375	1			T33	7		T34	150		T36	141
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	533926	1			T33	13		T34	14		T35	69
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2293424	1			T33	24		T34	40		T35	161
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	1995495	1			T33	5		T34	110		T35	104
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	538438	1			T33	11		T34	12		T35	66
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	562339	1			T33	51		T34	17		T35	49
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	283542	1			T33	9		T34	71		T36	126
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	535762	1			T33	23		T34	6		T35	38
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2285383	1			T33	70		T34	30		T35	148
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2002766	1			T33	9		T34	87		T35	83
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	536290	1			T33	22		T34	3		T35	56
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	565127	1			T33	11		T34	23		T35	78
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	288501	1			T34	97		T36	122		T37	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	530933	1			T33	11		T34	16		T35	53
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2288235	1			T33	55		T34	25		T35	172
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	1998431	1			T33	11		T34	61		T35	95
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	536799	1			T33	17		T34	11		T35	59
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	567258	1			T33	15		T34	30		T35	50
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	283079	1			T34	107		T36	148		T37	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	535198	1			T33	25		T34	22		T35	42
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2297551	1			T33	42		T34	53		T35	128
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	1992274	1			T33	7		T34	162		T35	107
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	538686	1			T33	7		T34	20		T35	64
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	564090	1			T33	42		T34	7		T35	46
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	283231	1			T33	2		T34	14		T36	176
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	533168	1			T33	23		T35	73		T36	112
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2285153	1			T33	8		T34	5		T35	154
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2001029	1			T34	7		T35	97		T36	148
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	538060	1			T33	9		T35	48		T36	152
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	566824	1			T33	73		T34	47		T35	63
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	283501	1			T33	12		T34	183		T36	118
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	534433	1			T33	21		T34	14		T35	56
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2283204	1			T33	37		T34	26		T35	147
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2005121	1			T34	104		T35	100		T36	150
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	537388	1			T33	13		T34	6		T35	64
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	566674	1			T33	46		T34	35		T35	55
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	284242	1			T33	13		T34	78		T36	147
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	532371	1			T33	14		T34	7		T35	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2287691	1			T33	34		T34	49		T35	152
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2002419	1			T33	12		T34	141		T35	95
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	537416	1			T33	8		T34	25		T35	55
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	563277	1			T33	48		T34	6		T35	62
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	282329	1			T33	3		T34	33		T36	125
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	535868	1			T33	18		T34	2		T35	54
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2287237	1			T33	29		T34	29		T35	141
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2003711	1			T33	4		T34	117		T35	103
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	538798	1			T33	17		T34	18		T35	62
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	561274	1			T33	50		T34	24		T35	50
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	282682	1			T33	12		T34	68		T36	138
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	535298	1			T33	11		T35	62		T36	130
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2283208	1			T33	36		T34	26		T35	157
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2006063	1			T33	2		T34	69		T35	94
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	539677	1			T33	17		T34	6		T35	52
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	564801	1			T33	53		T34	22		T35	51
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	282602	1			T33	7		T34	114		T36	119
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	532649	1			T33	8		T34	19		T35	64
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2285089	1			T33	34		T34	41		T35	140
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2004673	1			T33	1		T34	113		T35	109
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	539157	1			T33	24		T34	13		T35	49
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	564043	1			T33	46		T34	23		T35	52
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	283117	1			T33	12		T34	59		T36	97
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	532921	1			T33	6		T34	7		T35	68
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2292946	1			T33	75		T34	43		T35	184
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	1995283	1			T33	19		T34	181		T35	94
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	540682	1			T33	12		T34	10		T35	36
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	562497	1			T33	15		T34	8		T35	56
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	282810	1			T34	14		T36	132		T37	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	534782	1			T33	2		T35	48		T36	120
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2279263	1			T33	38		T34	63		T35	166
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2007156	1			T33	4		T34	162		T35	97
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	542797	1			T33	21		T34	27		T35	59
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	566466	1			T33	36		T35	50		T38	37
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	280134	1			T33	4		T34	4		T36	136
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	533184	1			T33	20		T35	46		T36	156
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2284863	1			T33	28		T34	26		T35	166
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2008414	1			T34	117		T35	107		T36	173
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	538777	1			T33	19		T34	7		T35	73
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	561504	1			T33	55		T34	18		T35	32
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	283009	1			T33	11		T34	78		T36	136
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	532433	1			T33	10		T34	10		T35	40
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2291149	1			T33	25		T34	19		T35	146
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	1997692	1			T33	2		T34	58		T35	119
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	538819	1			T33	20		T34	6		T35	37
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	563934	1			T33	50		T34	44		T35	52
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	283071	1			T33	10		T34	113		T36	125
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	534335	1			T33	16		T34	16		T35	64
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2280575	1			T33	40		T34	48		T35	177
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2009769	1			T33	8		T34	169		T35	104
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	534350	1			T33	13		T34	18		T35	54
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	567814	1			T33	39		T34	3		T35	52
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	284549	1			T33	3		T34	18		T36	163
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	531943	1			T33	20		T35	31		T36	104
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2284984	1			T33	56		T34	45		T35	155
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2006229	1			T33	8		T34	188		T35	100
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	535286	1			T33	15		T34	19		T35	44
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	564009	1			T33	29		T34	1		T35	62
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	285520	1			T33	3		T34	3		T36	173
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	532972	1			T33	12		T35	57		T36	130
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2285485	1			T33	30		T34	16		T35	173
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2010952	1			T33	5		T34	94		T35	96
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	533415	1			T33	2		T34	11		T35	65
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	563331	1			T33	61		T34	37		T35	44
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	284607	1			T33	13		T34	92		T36	108
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	531210	1			T33	12		T34	6		T35	40
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2276990	1			T33	71		T34	19		T35	149
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2013718	1			T33	9		T34	64		T35	97
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	537096	1			T33	12		T34	6		T35	68
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	563264	1			T33	19		T34	33		T35	44
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	284972	1			T33	1		T34	120		T36	114
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	532960	1			T33	11		T34	14		T35	60
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2290753	1			T33	40		T34	17		T35	158
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2005696	1			T33	9		T34	92		T35	89
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	536697	1			T33	9		T34	16		T35	64
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	563426	1			T33	45		T34	29		T35	43
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	282763	1			T33	3		T34	90		T36	134
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	529665	1			T33	17		T34	12		T35	64
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2288010	1			T33	66		T34	32		T35	165
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2000589	1			T33	6		T34	128		T35	105
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	537495	1			T33	14		T34	15		T35	44
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	564318	1			T33	28		T34	18		T35	40
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	287082	1			T33	3		T34	59		T36	134
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	531506	1			T33	6		T34	4		T35	64
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2290301	1			T33	19		T34	31		T35	139
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2001177	1			T33	2		T34	100		T35	111
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	537091	1			T34	9		T35	56		T36	154
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	564352	1			T33	53		T34	19		T35	56
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	286995	1			T33	14		T34	87		T36	113
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	529084	1			T33	35		T34	10		T35	56
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2280892	1			T33	67		T34	43		T35	149
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2010545	1			T33	5		T34	181		T35	106
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	535202	1			T33	6		T34	25		T35	59
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	569257	1			T33	37		T34	5		T35	46
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	282917	1			T33	8		T34	2		T36	156
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	530187	1			T35	58		T36	159		T37	2
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2289850	1			T33	34		T34	17		T35	152
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2003598	1			T33	9		T34	16		T35	94
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	535633	1			T33	19		T35	52		T36	140
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	567169	1			T33	47		T34	56		T35	56
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	283946	1			T33	2		T34	145		T36	152
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	528804	1			T33	12		T34	22		T35	64
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2282415	1			T33	60		T34	47		T35	143
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2009224	1			T33	1		T34	187		T35	114
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	538534	1			T33	25		T34	18		T35	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	562532	1			T33	27		T34	1		T35	73
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	284482	1			T33	3		T34	3		T36	120
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	531813	1			T33	7		T35	42		T36	164
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2294586	1			T33	53		T34	9		T35	153
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	1992944	1			T33	9		T34	24		T35	98
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	535848	1			T33	10		T35	59		T36	136
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	563113	1			T33	44		T34	42		T35	58
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	287842	1			T33	5		T34	155		T36	132
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	534667	1			T33	2		T34	26		T35	50
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2295317	1			T33	51		T34	59		T35	154
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	1997412	1			T33	1		T34	146		T35	107
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	537587	1			T33	17		T34	30		T35	46
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	563209	1			T33	32		T34	9		T35	69
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	282399	1			T33	14		T34	12		T36	106
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	533076	1			T33	8		T35	42		T36	138
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2284274	1			T33	66		T34	41		T35	154
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2009242	1			T33	10		T34	125		T35	101
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	535989	1			T33	21		T34	14		T35	68
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	562485	1			T33	20		T34	12		T35	42
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	285802	1			T33	1		T34	55		T36	138
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	531208	1			T33	5		T34	9		T35	53
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2287256	1			T33	45		T34	18		T35	173
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2006141	1			T33	4		T34	15		T35	76
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	537776	1			T33	13		T35	93		T36	146
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	562143	1			T33	39		T34	41		T35	32
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	284854	1			T33	8		T34	164		T36	144
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	530830	1			T33	14		T34	18		T35	44

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal