Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[1]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[2]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[3]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[4]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[5]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[6]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[7]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[8]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[9]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[10]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[11]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[12]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[13]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[14]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[15]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[16]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[17]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[18]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[19]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[20]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[21]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[22]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[23]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[24]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[25]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[26]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[27]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[28]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[29]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[30]	6209000	1			T33	123		T34	256		T35	418
bins_for_gpio_bits[31]	6209000	1			T33	123		T34	256		T35	418

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108452233

1

T33

3118

T34

2088

T35

8417

auto[1]

90235767

1

T33

818

T34

6104

T35

4959

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108443231

1

T33

3107

T34

2088

T35

8411

auto[1]

90244769

1

T33

829

T34

6104

T35

4965

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3293351	1			T33	95		T34	53		T35	238
bins_for_gpio_bits[0]	auto[0]	auto[1]	96500	1			T33	2		T34	2		T35	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	96765	1			T33	2		T34	2		T35	14
bins_for_gpio_bits[0]	auto[1]	auto[1]	2722384	1			T33	24		T34	199		T35	152
bins_for_gpio_bits[1]	auto[0]	auto[0]	3294066	1			T33	101		T34	59		T35	249
bins_for_gpio_bits[1]	auto[0]	auto[1]	96459	1			T33	2		T34	4		T35	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	96757	1			T33	2		T34	4		T35	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	2721718	1			T33	18		T34	189		T35	139
bins_for_gpio_bits[2]	auto[0]	auto[0]	3292288	1			T33	85		T34	42		T35	235
bins_for_gpio_bits[2]	auto[0]	auto[1]	96470	1			T33	3		T34	2		T35	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	96804	1			T33	3		T34	2		T35	13
bins_for_gpio_bits[2]	auto[1]	auto[1]	2723438	1			T33	32		T34	210		T35	157
bins_for_gpio_bits[3]	auto[0]	auto[0]	3299026	1			T33	91		T34	53		T35	220
bins_for_gpio_bits[3]	auto[0]	auto[1]	96488	1			T33	1		T34	1		T35	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	96779	1			T33	2		T34	1		T35	16
bins_for_gpio_bits[3]	auto[1]	auto[1]	2716707	1			T33	29		T34	201		T35	167
bins_for_gpio_bits[4]	auto[0]	auto[0]	3297725	1			T33	83		T34	65		T35	261
bins_for_gpio_bits[4]	auto[0]	auto[1]	96194	1			T33	3		T34	4		T35	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	96476	1			T33	3		T34	4		T35	15
bins_for_gpio_bits[4]	auto[1]	auto[1]	2718605	1			T33	34		T34	183		T35	127
bins_for_gpio_bits[5]	auto[0]	auto[0]	3290346	1			T33	101		T34	55		T35	266
bins_for_gpio_bits[5]	auto[0]	auto[1]	96201	1			T33	1		T34	1		T35	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	96454	1			T33	2		T34	1		T35	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	2725999	1			T33	19		T34	199		T35	121
bins_for_gpio_bits[6]	auto[0]	auto[0]	3295536	1			T33	84		T34	63		T35	271
bins_for_gpio_bits[6]	auto[0]	auto[1]	96502	1			T33	2		T34	3		T35	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	96756	1			T33	3		T34	3		T35	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	2720206	1			T33	34		T34	187		T35	127
bins_for_gpio_bits[7]	auto[0]	auto[0]	3303481	1			T33	89		T34	73		T35	222
bins_for_gpio_bits[7]	auto[0]	auto[1]	96589	1			T33	1		T34	7		T35	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	96846	1			T33	2		T34	7		T35	16
bins_for_gpio_bits[7]	auto[1]	auto[1]	2712084	1			T33	31		T34	169		T35	165
bins_for_gpio_bits[8]	auto[0]	auto[0]	3293331	1			T33	87		T34	52		T35	251
bins_for_gpio_bits[8]	auto[0]	auto[1]	96424	1			T33	3		T35	14		T36	35
bins_for_gpio_bits[8]	auto[1]	auto[0]	96706	1			T33	3		T35	14		T36	35
bins_for_gpio_bits[8]	auto[1]	auto[1]	2722539	1			T33	30		T34	204		T35	139
bins_for_gpio_bits[9]	auto[0]	auto[0]	3290590	1			T33	94		T34	64		T35	251
bins_for_gpio_bits[9]	auto[0]	auto[1]	96351	1			T33	1		T34	3		T35	15
bins_for_gpio_bits[9]	auto[1]	auto[0]	96676	1			T33	2		T34	3		T35	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	2725383	1			T33	26		T34	186		T35	137
bins_for_gpio_bits[10]	auto[0]	auto[0]	3291628	1			T33	87		T34	71		T35	252
bins_for_gpio_bits[10]	auto[0]	auto[1]	96490	1			T33	2		T34	9		T35	17
bins_for_gpio_bits[10]	auto[1]	auto[0]	96756	1			T33	3		T34	9		T35	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	2724126	1			T33	31		T34	167		T35	132
bins_for_gpio_bits[11]	auto[0]	auto[0]	3290755	1			T33	94		T34	65		T35	237
bins_for_gpio_bits[11]	auto[0]	auto[1]	96286	1			T33	2		T34	6		T35	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	96554	1			T33	2		T34	6		T35	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	2725405	1			T33	25		T34	179		T35	149
bins_for_gpio_bits[12]	auto[0]	auto[0]	3291344	1			T33	104		T34	52		T35	247
bins_for_gpio_bits[12]	auto[0]	auto[1]	96061	1			T33	2		T34	2		T35	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	96342	1			T33	2		T34	2		T35	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	2725253	1			T33	15		T34	200		T35	145
bins_for_gpio_bits[13]	auto[0]	auto[0]	3291460	1			T33	103		T34	72		T35	227
bins_for_gpio_bits[13]	auto[0]	auto[1]	96558	1			T33	1		T34	5		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	96829	1			T33	1		T34	5		T35	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	2724153	1			T33	18		T34	174		T35	163
bins_for_gpio_bits[14]	auto[0]	auto[0]	3299467	1			T33	101		T34	58		T35	264
bins_for_gpio_bits[14]	auto[0]	auto[1]	96371	1			T33	1		T34	3		T35	12
bins_for_gpio_bits[14]	auto[1]	auto[0]	96658	1			T33	1		T34	3		T35	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	2716504	1			T33	20		T34	192		T35	130
bins_for_gpio_bits[15]	auto[0]	auto[0]	3291800	1			T33	91		T34	81		T35	261
bins_for_gpio_bits[15]	auto[0]	auto[1]	96467	1			T33	3		T34	9		T35	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	96726	1			T33	4		T34	9		T35	14
bins_for_gpio_bits[15]	auto[1]	auto[1]	2724007	1			T33	25		T34	157		T35	129
bins_for_gpio_bits[16]	auto[0]	auto[0]	3288435	1			T33	99		T34	48		T35	262
bins_for_gpio_bits[16]	auto[0]	auto[1]	96397	1			T33	3		T34	3		T35	9
bins_for_gpio_bits[16]	auto[1]	auto[0]	96709	1			T33	3		T34	3		T35	9
bins_for_gpio_bits[16]	auto[1]	auto[1]	2727459	1			T33	18		T34	202		T35	138
bins_for_gpio_bits[17]	auto[0]	auto[0]	3297484	1			T33	91		T34	66		T35	224
bins_for_gpio_bits[17]	auto[0]	auto[1]	96150	1			T33	4		T34	3		T35	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	96418	1			T33	4		T34	3		T35	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	2718948	1			T33	24		T34	184		T35	172
bins_for_gpio_bits[18]	auto[0]	auto[0]	3285993	1			T33	89		T34	63		T35	272
bins_for_gpio_bits[18]	auto[0]	auto[1]	96450	1			T33	2		T34	6		T35	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	96746	1			T33	3		T34	6		T35	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	2729811	1			T33	29		T34	181		T35	125
bins_for_gpio_bits[19]	auto[0]	auto[0]	3287612	1			T33	98		T34	58		T35	248
bins_for_gpio_bits[19]	auto[0]	auto[1]	96379	1			T33	2		T34	7		T35	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	96667	1			T33	2		T34	7		T35	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	2728342	1			T33	21		T34	184		T35	145
bins_for_gpio_bits[20]	auto[0]	auto[0]	3285590	1			T33	90		T34	61		T35	270
bins_for_gpio_bits[20]	auto[0]	auto[1]	96360	1			T33	3		T34	3		T35	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	96641	1			T33	3		T34	3		T35	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	2730409	1			T33	27		T34	189		T35	124
bins_for_gpio_bits[21]	auto[0]	auto[0]	3280781	1			T33	100		T34	56		T35	247
bins_for_gpio_bits[21]	auto[0]	auto[1]	96283	1			T33	1		T34	2		T35	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	96569	1			T33	2		T34	2		T35	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	2735367	1			T33	20		T34	196		T35	143
bins_for_gpio_bits[22]	auto[0]	auto[0]	3294228	1			T33	92		T34	57		T35	253
bins_for_gpio_bits[22]	auto[0]	auto[1]	96350	1			T33	2		T34	5		T35	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	96648	1			T33	2		T34	5		T35	12
bins_for_gpio_bits[22]	auto[1]	auto[1]	2721774	1			T33	27		T34	189		T35	141
bins_for_gpio_bits[23]	auto[0]	auto[0]	3293579	1			T33	106		T34	60		T35	233
bins_for_gpio_bits[23]	auto[0]	auto[1]	95974	1			T33	2		T34	5		T35	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	96244	1			T33	2		T34	5		T35	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	2723203	1			T33	13		T34	186		T35	153
bins_for_gpio_bits[24]	auto[0]	auto[0]	3295055	1			T33	68		T34	56		T35	236
bins_for_gpio_bits[24]	auto[0]	auto[1]	96395	1			T33	3		T34	3		T35	15
bins_for_gpio_bits[24]	auto[1]	auto[0]	96689	1			T33	4		T34	3		T35	15
bins_for_gpio_bits[24]	auto[1]	auto[1]	2720861	1			T33	48		T34	194		T35	152
bins_for_gpio_bits[25]	auto[0]	auto[0]	3288522	1			T33	110		T34	64		T35	237
bins_for_gpio_bits[25]	auto[0]	auto[1]	96587	1			T34	9		T35	17		T36	26
bins_for_gpio_bits[25]	auto[1]	auto[0]	96829	1			T34	9		T35	17		T36	26
bins_for_gpio_bits[25]	auto[1]	auto[1]	2727062	1			T33	13		T34	174		T35	147
bins_for_gpio_bits[26]	auto[0]	auto[0]	3296294	1			T33	96		T34	73		T35	246
bins_for_gpio_bits[26]	auto[0]	auto[1]	96077	1			T33	4		T35	14		T36	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	96358	1			T33	4		T35	14		T36	28
bins_for_gpio_bits[26]	auto[1]	auto[1]	2720271	1			T33	19		T34	183		T35	144
bins_for_gpio_bits[27]	auto[0]	auto[0]	3287065	1			T33	110		T34	61		T35	248
bins_for_gpio_bits[27]	auto[0]	auto[1]	96120	1			T33	2		T34	5		T35	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	96416	1			T33	2		T34	5		T35	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	2729399	1			T33	9		T34	185		T35	142
bins_for_gpio_bits[28]	auto[0]	auto[0]	3296999	1			T33	106		T34	51		T35	256
bins_for_gpio_bits[28]	auto[0]	auto[1]	96265	1			T33	1		T35	14		T36	37
bins_for_gpio_bits[28]	auto[1]	auto[0]	96548	1			T33	1		T35	14		T36	37
bins_for_gpio_bits[28]	auto[1]	auto[1]	2719188	1			T33	15		T34	205		T35	134
bins_for_gpio_bits[29]	auto[0]	auto[0]	3299186	1			T33	97		T34	88		T35	257
bins_for_gpio_bits[29]	auto[0]	auto[1]	96684	1			T33	3		T34	10		T35	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	96927	1			T33	3		T34	10		T35	12
bins_for_gpio_bits[29]	auto[1]	auto[1]	2716203	1			T33	20		T34	148		T35	137
bins_for_gpio_bits[30]	auto[0]	auto[0]	3286199	1			T33	105		T34	62		T35	249
bins_for_gpio_bits[30]	auto[0]	auto[1]	96273	1			T33	1		T34	5		T35	14
bins_for_gpio_bits[30]	auto[1]	auto[0]	96549	1			T33	2		T34	5		T35	15
bins_for_gpio_bits[30]	auto[1]	auto[1]	2729979	1			T33	15		T34	184		T35	140
bins_for_gpio_bits[31]	auto[0]	auto[0]	3290646	1			T33	94		T34	59		T35	284
bins_for_gpio_bits[31]	auto[0]	auto[1]	96214	1			T33	3		T35	14		T36	34
bins_for_gpio_bits[31]	auto[1]	auto[0]	96529	1			T33	3		T35	14		T36	34
bins_for_gpio_bits[31]	auto[1]	auto[1]	2725611	1			T33	23		T34	197		T35	106