Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4144710 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2086651 |
1 |
|
|
T37 |
23 |
|
T39 |
117 |
|
T41 |
284 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5968423 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
262938 |
1 |
|
|
T37 |
1 |
|
T39 |
8 |
|
T41 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4138916 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2092445 |
1 |
|
|
T37 |
13 |
|
T39 |
140 |
|
T41 |
349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
918337 |
1 |
|
|
T39 |
80 |
|
T41 |
218 |
|
T66 |
761 |
| auto[1] |
auto[0] |
auto[1] |
132035 |
1 |
|
|
T39 |
4 |
|
T41 |
4 |
|
T66 |
183 |
| auto[1] |
auto[1] |
auto[0] |
911170 |
1 |
|
|
T37 |
12 |
|
T39 |
52 |
|
T41 |
118 |
| auto[1] |
auto[1] |
auto[1] |
130903 |
1 |
|
|
T37 |
1 |
|
T39 |
4 |
|
T41 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |