Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4143699 1 T33 63 T34 143 T35 308
auto[1] 2087662 1 T37 8 T39 85 T41 543


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 5292566 1 T33 63 T34 143 T35 308
auto[1] 938795 1 T37 7 T39 68 T41 43


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4157699 1 T33 63 T34 143 T35 308
auto[1] 2073662 1 T37 9 T39 89 T41 230


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_en   intr_en   intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[1] auto[0] auto[0] 567479 1 T37 2 T39 18 T41 48
auto[1] auto[0] auto[1] 467343 1 T37 7 T39 50 T41 21
auto[1] auto[1] auto[0] 567388 1 T39 3 T41 139 T66 327
auto[1] auto[1] auto[1] 471452 1 T39 18 T41 22 T66 319


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded