Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4130192 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2101169 |
1 |
|
|
T37 |
23 |
|
T39 |
106 |
|
T41 |
429 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5281896 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
949465 |
1 |
|
|
T39 |
72 |
|
T41 |
51 |
|
T66 |
899 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4132030 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2099331 |
1 |
|
|
T39 |
152 |
|
T41 |
279 |
|
T66 |
1766 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
566968 |
1 |
|
|
T39 |
37 |
|
T41 |
50 |
|
T66 |
402 |
| auto[1] |
auto[0] |
auto[1] |
472027 |
1 |
|
|
T39 |
47 |
|
T41 |
24 |
|
T66 |
407 |
| auto[1] |
auto[1] |
auto[0] |
582898 |
1 |
|
|
T39 |
43 |
|
T41 |
178 |
|
T66 |
465 |
| auto[1] |
auto[1] |
auto[1] |
477438 |
1 |
|
|
T39 |
25 |
|
T41 |
27 |
|
T66 |
492 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |