Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4149513 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2081848 |
1 |
|
|
T39 |
154 |
|
T41 |
317 |
|
T66 |
1584 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5289628 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
941733 |
1 |
|
|
T39 |
42 |
|
T41 |
78 |
|
T66 |
941 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4145890 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2085471 |
1 |
|
|
T39 |
142 |
|
T41 |
450 |
|
T66 |
1809 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
573259 |
1 |
|
|
T39 |
54 |
|
T41 |
235 |
|
T66 |
446 |
| auto[1] |
auto[0] |
auto[1] |
473005 |
1 |
|
|
T39 |
16 |
|
T41 |
48 |
|
T66 |
508 |
| auto[1] |
auto[1] |
auto[0] |
570479 |
1 |
|
|
T39 |
46 |
|
T41 |
137 |
|
T66 |
422 |
| auto[1] |
auto[1] |
auto[1] |
468728 |
1 |
|
|
T39 |
26 |
|
T41 |
30 |
|
T66 |
433 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |