Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4166715 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2064646 |
1 |
|
|
T37 |
18 |
|
T39 |
89 |
|
T41 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5286631 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
944730 |
1 |
|
|
T39 |
94 |
|
T41 |
122 |
|
T66 |
925 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4141929 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2089432 |
1 |
|
|
T37 |
1 |
|
T39 |
149 |
|
T41 |
341 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
580759 |
1 |
|
|
T39 |
41 |
|
T41 |
101 |
|
T66 |
491 |
| auto[1] |
auto[0] |
auto[1] |
476427 |
1 |
|
|
T39 |
69 |
|
T41 |
78 |
|
T66 |
505 |
| auto[1] |
auto[1] |
auto[0] |
563943 |
1 |
|
|
T37 |
1 |
|
T39 |
14 |
|
T41 |
118 |
| auto[1] |
auto[1] |
auto[1] |
468303 |
1 |
|
|
T39 |
25 |
|
T41 |
44 |
|
T66 |
420 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |