Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4147706 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2083655 |
1 |
|
|
T37 |
8 |
|
T39 |
124 |
|
T41 |
358 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5292884 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
938477 |
1 |
|
|
T37 |
6 |
|
T39 |
92 |
|
T41 |
110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4151501 |
1 |
|
|
T33 |
63 |
|
T34 |
143 |
|
T35 |
308 |
| auto[1] |
2079860 |
1 |
|
|
T37 |
6 |
|
T39 |
148 |
|
T41 |
518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
574808 |
1 |
|
|
T39 |
37 |
|
T41 |
227 |
|
T66 |
263 |
| auto[1] |
auto[0] |
auto[1] |
469393 |
1 |
|
|
T37 |
6 |
|
T39 |
44 |
|
T41 |
67 |
| auto[1] |
auto[1] |
auto[0] |
566575 |
1 |
|
|
T39 |
19 |
|
T41 |
181 |
|
T66 |
362 |
| auto[1] |
auto[1] |
auto[1] |
469084 |
1 |
|
|
T39 |
48 |
|
T41 |
43 |
|
T66 |
362 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |