Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1519833	1			T33	1		T34	1		T35	1
all_pins[1]	1519833	1			T33	1		T34	1		T35	1
all_pins[2]	1519833	1			T33	1		T34	1		T35	1
all_pins[3]	1519833	1			T33	1		T34	1		T35	1
all_pins[4]	1519833	1			T33	1		T34	1		T35	1
all_pins[5]	1519833	1			T33	1		T34	1		T35	1
all_pins[6]	1519833	1			T33	1		T34	1		T35	1
all_pins[7]	1519833	1			T33	1		T34	1		T35	1
all_pins[8]	1519833	1			T33	1		T34	1		T35	1
all_pins[9]	1519833	1			T33	1		T34	1		T35	1
all_pins[10]	1519833	1			T33	1		T34	1		T35	1
all_pins[11]	1519833	1			T33	1		T34	1		T35	1
all_pins[12]	1519833	1			T33	1		T34	1		T35	1
all_pins[13]	1519833	1			T33	1		T34	1		T35	1
all_pins[14]	1519833	1			T33	1		T34	1		T35	1
all_pins[15]	1519833	1			T33	1		T34	1		T35	1
all_pins[16]	1519833	1			T33	1		T34	1		T35	1
all_pins[17]	1519833	1			T33	1		T34	1		T35	1
all_pins[18]	1519833	1			T33	1		T34	1		T35	1
all_pins[19]	1519833	1			T33	1		T34	1		T35	1
all_pins[20]	1519833	1			T33	1		T34	1		T35	1
all_pins[21]	1519833	1			T33	1		T34	1		T35	1
all_pins[22]	1519833	1			T33	1		T34	1		T35	1
all_pins[23]	1519833	1			T33	1		T34	1		T35	1
all_pins[24]	1519833	1			T33	1		T34	1		T35	1
all_pins[25]	1519833	1			T33	1		T34	1		T35	1
all_pins[26]	1519833	1			T33	1		T34	1		T35	1
all_pins[27]	1519833	1			T33	1		T34	1		T35	1
all_pins[28]	1519833	1			T33	1		T34	1		T35	1
all_pins[29]	1519833	1			T33	1		T34	1		T35	1
all_pins[30]	1519833	1			T33	1		T34	1		T35	1
all_pins[31]	1519833	1			T33	1		T34	1		T35	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30231158	1			T33	32		T34	32		T35	32
values[0x1]	18403498	1			T38	1806		T39	6529		T21	465
transitions[0x0=>0x1]	11020253	1			T38	1087		T39	3889		T21	308
transitions[0x1=>0x0]	11020090	1			T38	1087		T39	3889		T21	308

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	945290	1			T33	1		T34	1		T35	1
all_pins[0]	values[0x1]	574543	1			T38	39		T39	179		T21	17
all_pins[0]	transitions[0x0=>0x1]	354858	1			T38	20		T39	104		T21	17
all_pins[0]	transitions[0x1=>0x0]	357429	1			T38	54		T39	104		T21	14
all_pins[1]	values[0x0]	944378	1			T33	1		T34	1		T35	1
all_pins[1]	values[0x1]	575455	1			T38	51		T39	215		T21	10
all_pins[1]	transitions[0x0=>0x1]	344486	1			T38	30		T39	116		T21	10
all_pins[1]	transitions[0x1=>0x0]	343574	1			T38	18		T39	80		T21	17
all_pins[2]	values[0x0]	946406	1			T33	1		T34	1		T35	1
all_pins[2]	values[0x1]	573427	1			T38	53		T39	126		T21	21
all_pins[2]	transitions[0x0=>0x1]	341900	1			T38	34		T39	89		T21	11
all_pins[2]	transitions[0x1=>0x0]	343928	1			T38	32		T39	178		T25	11
all_pins[3]	values[0x0]	944063	1			T33	1		T34	1		T35	1
all_pins[3]	values[0x1]	575770	1			T38	57		T39	267		T21	5
all_pins[3]	transitions[0x0=>0x1]	346719	1			T38	40		T39	211		T21	1
all_pins[3]	transitions[0x1=>0x0]	344376	1			T38	36		T39	70		T21	17
all_pins[4]	values[0x0]	941199	1			T33	1		T34	1		T35	1
all_pins[4]	values[0x1]	578634	1			T38	76		T39	269		T21	11
all_pins[4]	transitions[0x0=>0x1]	344955	1			T38	43		T39	142		T21	9
all_pins[4]	transitions[0x1=>0x0]	342091	1			T38	24		T39	140		T21	3
all_pins[5]	values[0x0]	941164	1			T33	1		T34	1		T35	1
all_pins[5]	values[0x1]	578669	1			T38	46		T39	152		T21	16
all_pins[5]	transitions[0x0=>0x1]	345599	1			T38	24		T39	73		T21	11
all_pins[5]	transitions[0x1=>0x0]	345564	1			T38	54		T39	190		T21	6
all_pins[6]	values[0x0]	946988	1			T33	1		T34	1		T35	1
all_pins[6]	values[0x1]	572845	1			T38	66		T39	218		T21	25
all_pins[6]	transitions[0x0=>0x1]	340283	1			T38	38		T39	146		T21	18
all_pins[6]	transitions[0x1=>0x0]	346107	1			T38	18		T39	80		T21	9
all_pins[7]	values[0x0]	946716	1			T33	1		T34	1		T35	1
all_pins[7]	values[0x1]	573117	1			T38	65		T39	179		T21	24
all_pins[7]	transitions[0x0=>0x1]	342937	1			T38	36		T39	71		T21	17
all_pins[7]	transitions[0x1=>0x0]	342665	1			T38	37		T39	110		T21	18
all_pins[8]	values[0x0]	942947	1			T33	1		T34	1		T35	1
all_pins[8]	values[0x1]	576886	1			T38	48		T39	158		T21	12
all_pins[8]	transitions[0x0=>0x1]	345794	1			T38	32		T39	109		T21	9
all_pins[8]	transitions[0x1=>0x0]	342025	1			T38	49		T39	130		T21	21
all_pins[9]	values[0x0]	942513	1			T33	1		T34	1		T35	1
all_pins[9]	values[0x1]	577320	1			T38	47		T39	263		T21	12
all_pins[9]	transitions[0x0=>0x1]	344649	1			T38	28		T39	210		T21	9
all_pins[9]	transitions[0x1=>0x0]	344215	1			T38	29		T39	105		T21	9
all_pins[10]	values[0x0]	944536	1			T33	1		T34	1		T35	1
all_pins[10]	values[0x1]	575297	1			T38	89		T39	176		T21	7
all_pins[10]	transitions[0x0=>0x1]	341529	1			T38	58		T39	75		T21	5
all_pins[10]	transitions[0x1=>0x0]	343552	1			T38	16		T39	162		T21	10
all_pins[11]	values[0x0]	942548	1			T33	1		T34	1		T35	1
all_pins[11]	values[0x1]	577285	1			T38	55		T39	212		T21	8
all_pins[11]	transitions[0x0=>0x1]	346123	1			T38	20		T39	135		T21	4
all_pins[11]	transitions[0x1=>0x0]	344135	1			T38	54		T39	99		T21	3
all_pins[12]	values[0x0]	945313	1			T33	1		T34	1		T35	1
all_pins[12]	values[0x1]	574520	1			T38	47		T39	206		T21	15
all_pins[12]	transitions[0x0=>0x1]	341391	1			T38	25		T39	115		T21	12
all_pins[12]	transitions[0x1=>0x0]	344156	1			T38	33		T39	121		T21	5
all_pins[13]	values[0x0]	946932	1			T33	1		T34	1		T35	1
all_pins[13]	values[0x1]	572901	1			T38	62		T39	214		T21	10
all_pins[13]	transitions[0x0=>0x1]	342982	1			T38	44		T39	135		T21	8
all_pins[13]	transitions[0x1=>0x0]	344601	1			T38	29		T39	127		T21	13
all_pins[14]	values[0x0]	943651	1			T33	1		T34	1		T35	1
all_pins[14]	values[0x1]	576182	1			T38	71		T39	213		T21	7
all_pins[14]	transitions[0x0=>0x1]	344357	1			T38	34		T39	107		T21	5
all_pins[14]	transitions[0x1=>0x0]	341076	1			T38	25		T39	108		T21	8
all_pins[15]	values[0x0]	946295	1			T33	1		T34	1		T35	1
all_pins[15]	values[0x1]	573538	1			T38	54		T39	172		T21	24
all_pins[15]	transitions[0x0=>0x1]	342808	1			T38	29		T39	119		T21	21
all_pins[15]	transitions[0x1=>0x0]	345452	1			T38	46		T39	160		T21	4
all_pins[16]	values[0x0]	942957	1			T33	1		T34	1		T35	1
all_pins[16]	values[0x1]	576876	1			T38	63		T39	293		T21	11
all_pins[16]	transitions[0x0=>0x1]	345877	1			T38	38		T39	200		T21	5
all_pins[16]	transitions[0x1=>0x0]	342539	1			T38	29		T39	79		T21	18
all_pins[17]	values[0x0]	943759	1			T33	1		T34	1		T35	1
all_pins[17]	values[0x1]	576074	1			T38	48		T39	192		T21	27
all_pins[17]	transitions[0x0=>0x1]	345239	1			T38	26		T39	61		T21	21
all_pins[17]	transitions[0x1=>0x0]	346041	1			T38	41		T39	162		T21	5
all_pins[18]	values[0x0]	945800	1			T33	1		T34	1		T35	1
all_pins[18]	values[0x1]	574033	1			T38	82		T39	283		T21	20
all_pins[18]	transitions[0x0=>0x1]	342987	1			T38	54		T39	157		T21	7
all_pins[18]	transitions[0x1=>0x0]	345028	1			T38	20		T39	66		T21	14
all_pins[19]	values[0x0]	949901	1			T33	1		T34	1		T35	1
all_pins[19]	values[0x1]	569932	1			T38	46		T39	243		T21	17
all_pins[19]	transitions[0x0=>0x1]	341802	1			T38	21		T39	120		T21	8
all_pins[19]	transitions[0x1=>0x0]	345903	1			T38	57		T39	160		T21	11
all_pins[20]	values[0x0]	944434	1			T33	1		T34	1		T35	1
all_pins[20]	values[0x1]	575399	1			T38	34		T39	223		T21	19
all_pins[20]	transitions[0x0=>0x1]	346568	1			T38	29		T39	107		T21	12
all_pins[20]	transitions[0x1=>0x0]	341101	1			T38	41		T39	127		T21	10
all_pins[21]	values[0x0]	944331	1			T33	1		T34	1		T35	1
all_pins[21]	values[0x1]	575502	1			T38	49		T39	200		T21	9
all_pins[21]	transitions[0x0=>0x1]	344138	1			T38	41		T39	129		T21	7
all_pins[21]	transitions[0x1=>0x0]	344035	1			T38	26		T39	152		T21	17
all_pins[22]	values[0x0]	943795	1			T33	1		T34	1		T35	1
all_pins[22]	values[0x1]	576038	1			T38	66		T39	166		T21	10
all_pins[22]	transitions[0x0=>0x1]	344028	1			T38	47		T39	84		T21	6
all_pins[22]	transitions[0x1=>0x0]	343492	1			T38	30		T39	118		T21	5
all_pins[23]	values[0x0]	947389	1			T33	1		T34	1		T35	1
all_pins[23]	values[0x1]	572444	1			T38	34		T39	205		T21	12
all_pins[23]	transitions[0x0=>0x1]	341975	1			T38	16		T39	140		T21	9
all_pins[23]	transitions[0x1=>0x0]	345569	1			T38	48		T39	101		T21	7
all_pins[24]	values[0x0]	945500	1			T33	1		T34	1		T35	1
all_pins[24]	values[0x1]	574333	1			T38	45		T39	183		T21	13
all_pins[24]	transitions[0x0=>0x1]	343777	1			T38	31		T39	123		T21	10
all_pins[24]	transitions[0x1=>0x0]	341888	1			T38	20		T39	145		T21	9
all_pins[25]	values[0x0]	945136	1			T33	1		T34	1		T35	1
all_pins[25]	values[0x1]	574697	1			T38	53		T39	186		T21	16
all_pins[25]	transitions[0x0=>0x1]	345654	1			T38	36		T39	119		T21	7
all_pins[25]	transitions[0x1=>0x0]	345290	1			T38	28		T39	116		T21	4
all_pins[26]	values[0x0]	945377	1			T33	1		T34	1		T35	1
all_pins[26]	values[0x1]	574456	1			T38	73		T39	212		T21	27
all_pins[26]	transitions[0x0=>0x1]	344323	1			T38	45		T39	125		T21	13
all_pins[26]	transitions[0x1=>0x0]	344564	1			T38	25		T39	99		T21	2
all_pins[27]	values[0x0]	944851	1			T33	1		T34	1		T35	1
all_pins[27]	values[0x1]	574982	1			T38	50		T39	237		T21	9
all_pins[27]	transitions[0x0=>0x1]	344176	1			T38	23		T39	144		T21	5
all_pins[27]	transitions[0x1=>0x0]	343650	1			T38	46		T39	119		T21	23
all_pins[28]	values[0x0]	942525	1			T33	1		T34	1		T35	1
all_pins[28]	values[0x1]	577308	1			T38	48		T39	201		T21	10
all_pins[28]	transitions[0x0=>0x1]	346368	1			T38	38		T39	107		T21	7
all_pins[28]	transitions[0x1=>0x0]	344042	1			T38	40		T39	143		T21	6
all_pins[29]	values[0x0]	942436	1			T33	1		T34	1		T35	1
all_pins[29]	values[0x1]	577397	1			T38	52		T39	157		T21	14
all_pins[29]	transitions[0x0=>0x1]	343439	1			T38	28		T39	117		T21	9
all_pins[29]	transitions[0x1=>0x0]	343350	1			T38	24		T39	161		T21	5
all_pins[30]	values[0x0]	949472	1			T33	1		T34	1		T35	1
all_pins[30]	values[0x1]	570361	1			T38	64		T39	150		T21	13
all_pins[30]	transitions[0x0=>0x1]	340285	1			T38	41		T39	73		T21	10
all_pins[30]	transitions[0x1=>0x0]	347321	1			T38	29		T39	80		T21	11
all_pins[31]	values[0x0]	942556	1			T33	1		T34	1		T35	1
all_pins[31]	values[0x1]	577277	1			T38	73		T39	179		T21	14
all_pins[31]	transitions[0x0=>0x1]	348247	1			T38	38		T39	126		T21	5
all_pins[31]	transitions[0x1=>0x0]	341331	1			T38	29		T39	97		T21	4