Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6400994	1			T33	357		T34	405		T35	413
all_values[1]	6400994	1			T33	357		T34	405		T35	413
all_values[2]	6400994	1			T33	357		T34	405		T35	413
all_values[3]	6400994	1			T33	357		T34	405		T35	413
all_values[4]	6400994	1			T33	357		T34	405		T35	413
all_values[5]	6400994	1			T33	357		T34	405		T35	413
all_values[6]	6400994	1			T33	357		T34	405		T35	413
all_values[7]	6400994	1			T33	357		T34	405		T35	413
all_values[8]	6400994	1			T33	357		T34	405		T35	413
all_values[9]	6400994	1			T33	357		T34	405		T35	413
all_values[10]	6400994	1			T33	357		T34	405		T35	413
all_values[11]	6400994	1			T33	357		T34	405		T35	413
all_values[12]	6400994	1			T33	357		T34	405		T35	413
all_values[13]	6400994	1			T33	357		T34	405		T35	413
all_values[14]	6400994	1			T33	357		T34	405		T35	413
all_values[15]	6400994	1			T33	357		T34	405		T35	413
all_values[16]	6400994	1			T33	357		T34	405		T35	413
all_values[17]	6400994	1			T33	357		T34	405		T35	413
all_values[18]	6400994	1			T33	357		T34	405		T35	413
all_values[19]	6400994	1			T33	357		T34	405		T35	413
all_values[20]	6400994	1			T33	357		T34	405		T35	413
all_values[21]	6400994	1			T33	357		T34	405		T35	413
all_values[22]	6400994	1			T33	357		T34	405		T35	413
all_values[23]	6400994	1			T33	357		T34	405		T35	413
all_values[24]	6400994	1			T33	357		T34	405		T35	413
all_values[25]	6400994	1			T33	357		T34	405		T35	413
all_values[26]	6400994	1			T33	357		T34	405		T35	413
all_values[27]	6400994	1			T33	357		T34	405		T35	413
all_values[28]	6400994	1			T33	357		T34	405		T35	413
all_values[29]	6400994	1			T33	357		T34	405		T35	413
all_values[30]	6400994	1			T33	357		T34	405		T35	413
all_values[31]	6400994	1			T33	357		T34	405		T35	413

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137531605

1

T33

11424

T34

12960

T35

13216

auto[1]

67300203

1

T38

3916

T39

18681

T21

1076

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83243284

1

T33

11424

T34

12960

T35

13216

auto[1]

121588524

1

T38

6399

T39

34167

T21

1188

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

202877786

1

T33

11424

T34

12960

T35

13216

auto[1]

1954022

1

T21

174

T40

65

T1

2789

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2389439	1			T33	357		T34	405		T35	413
all_values[0]	auto[0]	auto[0]	auto[1]	1876505	1			T38	114		T39	635		T21	36
all_values[0]	auto[0]	auto[1]	auto[0]	212612	1			T38	18		T39	39		T21	12
all_values[0]	auto[0]	auto[1]	auto[1]	1861610	1			T38	80		T39	423		T21	15
all_values[0]	auto[1]	auto[0]	auto[1]	30612	1			T21	2		T1	46		T104	1
all_values[0]	auto[1]	auto[1]	auto[1]	30216	1			T21	2		T1	49		T104	1
all_values[1]	auto[0]	auto[0]	auto[0]	2390059	1			T33	357		T34	405		T35	413
all_values[1]	auto[0]	auto[0]	auto[1]	1872727	1			T38	112		T39	516		T21	17
all_values[1]	auto[0]	auto[1]	auto[0]	212962	1			T38	6		T39	37		T21	18
all_values[1]	auto[0]	auto[1]	auto[1]	1864138	1			T38	94		T39	536		T21	8
all_values[1]	auto[1]	auto[0]	auto[1]	30781	1			T21	4		T40	2		T1	45
all_values[1]	auto[1]	auto[1]	auto[1]	30327	1			T21	3		T40	2		T1	44
all_values[2]	auto[0]	auto[0]	auto[0]	2391261	1			T33	357		T34	405		T35	413
all_values[2]	auto[0]	auto[0]	auto[1]	1888490	1			T38	96		T39	678		T21	11
all_values[2]	auto[0]	auto[1]	auto[0]	207328	1			T38	27		T39	47		T21	19
all_values[2]	auto[0]	auto[1]	auto[1]	1852902	1			T38	100		T39	386		T21	19
all_values[2]	auto[1]	auto[0]	auto[1]	30934	1			T21	1		T40	1		T1	55
all_values[2]	auto[1]	auto[1]	auto[1]	30079	1			T21	4		T40	1		T1	32
all_values[3]	auto[0]	auto[0]	auto[0]	2389014	1			T33	357		T34	405		T35	413
all_values[3]	auto[0]	auto[0]	auto[1]	1872714	1			T38	98		T39	395		T21	17
all_values[3]	auto[0]	auto[1]	auto[0]	210059	1			T38	19		T39	72		T21	14
all_values[3]	auto[0]	auto[1]	auto[1]	1867955	1			T38	107		T39	666		T21	4
all_values[3]	auto[1]	auto[0]	auto[1]	30878	1			T21	3		T40	2		T1	50
all_values[3]	auto[1]	auto[1]	auto[1]	30374	1			T21	1		T40	1		T1	39
all_values[4]	auto[0]	auto[0]	auto[0]	2389868	1			T33	357		T34	405		T35	413
all_values[4]	auto[0]	auto[0]	auto[1]	1867280	1			T38	73		T39	480		T21	19
all_values[4]	auto[0]	auto[1]	auto[0]	212146	1			T38	28		T39	41		T21	20
all_values[4]	auto[0]	auto[1]	auto[1]	1870464	1			T38	126		T39	632		T21	6
all_values[4]	auto[1]	auto[0]	auto[1]	30832	1			T21	3		T40	2		T1	57
all_values[4]	auto[1]	auto[1]	auto[1]	30404	1			T21	3		T40	1		T1	44
all_values[5]	auto[0]	auto[0]	auto[0]	2389757	1			T33	357		T34	405		T35	413
all_values[5]	auto[0]	auto[0]	auto[1]	1877013	1			T38	130		T39	687		T21	19
all_values[5]	auto[0]	auto[1]	auto[0]	209593	1			T38	9		T39	68		T21	8
all_values[5]	auto[0]	auto[1]	auto[1]	1863892	1			T38	91		T39	363		T21	15
all_values[5]	auto[1]	auto[0]	auto[1]	30539	1			T21	3		T1	39		T104	2
all_values[5]	auto[1]	auto[1]	auto[1]	30200	1			T21	1		T40	2		T1	38
all_values[6]	auto[0]	auto[0]	auto[0]	2387769	1			T33	357		T34	405		T35	413
all_values[6]	auto[0]	auto[0]	auto[1]	1885074	1			T38	75		T39	484		T21	19
all_values[6]	auto[0]	auto[1]	auto[0]	212264	1			T38	19		T39	85		T21	18
all_values[6]	auto[0]	auto[1]	auto[1]	1855087	1			T38	113		T39	590		T21	18
all_values[6]	auto[1]	auto[0]	auto[1]	30569	1			T21	4		T40	1		T1	49
all_values[6]	auto[1]	auto[1]	auto[1]	30231	1			T21	4		T40	1		T1	33
all_values[7]	auto[0]	auto[0]	auto[0]	2390166	1			T33	357		T34	405		T35	413
all_values[7]	auto[0]	auto[0]	auto[1]	1884036	1			T38	75		T39	614		T21	18
all_values[7]	auto[0]	auto[1]	auto[0]	210871	1			T38	20		T39	55		T21	19
all_values[7]	auto[0]	auto[1]	auto[1]	1854846	1			T38	119		T39	428		T21	23
all_values[7]	auto[1]	auto[0]	auto[1]	31009	1			T21	2		T1	34		T2	46
all_values[7]	auto[1]	auto[1]	auto[1]	30066	1			T21	5		T40	2		T1	46
all_values[8]	auto[0]	auto[0]	auto[0]	2388524	1			T33	357		T34	405		T35	413
all_values[8]	auto[0]	auto[0]	auto[1]	1884325	1			T38	98		T39	637		T21	16
all_values[8]	auto[0]	auto[1]	auto[0]	211965	1			T38	27		T39	77		T21	33
all_values[8]	auto[0]	auto[1]	auto[1]	1855200	1			T38	92		T39	442		T21	9
all_values[8]	auto[1]	auto[0]	auto[1]	30540	1			T21	3		T1	46		T104	1
all_values[8]	auto[1]	auto[1]	auto[1]	30440	1			T21	2		T40	1		T1	46
all_values[9]	auto[0]	auto[0]	auto[0]	2391666	1			T33	357		T34	405		T35	413
all_values[9]	auto[0]	auto[0]	auto[1]	1867359	1			T38	76		T39	411		T21	37
all_values[9]	auto[0]	auto[1]	auto[0]	213045	1			T38	32		T39	78		T21	7
all_values[9]	auto[0]	auto[1]	auto[1]	1867869	1			T38	99		T39	669		T21	10
all_values[9]	auto[1]	auto[0]	auto[1]	30678	1			T21	2		T40	2		T1	40
all_values[9]	auto[1]	auto[1]	auto[1]	30377	1			T21	2		T1	47		T2	43
all_values[10]	auto[0]	auto[0]	auto[0]	2390728	1			T33	357		T34	405		T35	413
all_values[10]	auto[0]	auto[0]	auto[1]	1875147	1			T38	69		T39	595		T21	21
all_values[10]	auto[0]	auto[1]	auto[0]	209721	1			T38	7		T39	59		T21	8
all_values[10]	auto[0]	auto[1]	auto[1]	1864229	1			T38	154		T39	459		T21	9
all_values[10]	auto[1]	auto[0]	auto[1]	30784	1			T21	4		T1	43		T2	46
all_values[10]	auto[1]	auto[1]	auto[1]	30385	1			T21	1		T40	3		T1	36
all_values[11]	auto[0]	auto[0]	auto[0]	2390731	1			T33	357		T34	405		T35	413
all_values[11]	auto[0]	auto[0]	auto[1]	1857543	1			T38	87		T39	532		T21	22
all_values[11]	auto[0]	auto[1]	auto[0]	210135	1			T38	23		T39	20		T21	19
all_values[11]	auto[0]	auto[1]	auto[1]	1881417	1			T38	116		T39	585		T21	7
all_values[11]	auto[1]	auto[0]	auto[1]	30701	1			T21	2		T1	44		T104	1
all_values[11]	auto[1]	auto[1]	auto[1]	30467	1			T21	2		T40	1		T1	47
all_values[12]	auto[0]	auto[0]	auto[0]	2389537	1			T33	357		T34	405		T35	413
all_values[12]	auto[0]	auto[0]	auto[1]	1882930	1			T38	111		T39	518		T21	33
all_values[12]	auto[0]	auto[1]	auto[0]	209367	1			T38	11		T39	29		T21	18
all_values[12]	auto[0]	auto[1]	auto[1]	1858371	1			T38	93		T39	530		T21	14
all_values[12]	auto[1]	auto[0]	auto[1]	30669	1			T21	4		T40	3		T1	52
all_values[12]	auto[1]	auto[1]	auto[1]	30120	1			T21	2		T40	1		T1	35
all_values[13]	auto[0]	auto[0]	auto[0]	2387982	1			T33	357		T34	405		T35	413
all_values[13]	auto[0]	auto[0]	auto[1]	1881693	1			T38	100		T39	557		T21	20
all_values[13]	auto[0]	auto[1]	auto[0]	210108	1			T38	10		T39	32		T21	4
all_values[13]	auto[0]	auto[1]	auto[1]	1859975	1			T38	99		T39	540		T21	10
all_values[13]	auto[1]	auto[0]	auto[1]	30969	1			T21	4		T40	1		T1	45
all_values[13]	auto[1]	auto[1]	auto[1]	30267	1			T21	1		T40	1		T1	41
all_values[14]	auto[0]	auto[0]	auto[0]	2392959	1			T33	357		T34	405		T35	413
all_values[14]	auto[0]	auto[0]	auto[1]	1874827	1			T38	57		T39	554		T21	14
all_values[14]	auto[0]	auto[1]	auto[0]	206800	1			T38	21		T39	68		T21	30
all_values[14]	auto[0]	auto[1]	auto[1]	1865358	1			T38	134		T39	496		T21	8
all_values[14]	auto[1]	auto[0]	auto[1]	30729	1			T40	1		T1	43		T104	1
all_values[14]	auto[1]	auto[1]	auto[1]	30321	1			T21	3		T40	3		T1	38
all_values[15]	auto[0]	auto[0]	auto[0]	2387788	1			T33	357		T34	405		T35	413
all_values[15]	auto[0]	auto[0]	auto[1]	1883806	1			T38	79		T39	655		T21	13
all_values[15]	auto[0]	auto[1]	auto[0]	214494	1			T38	21		T39	26		T21	12
all_values[15]	auto[0]	auto[1]	auto[1]	1853705	1			T38	102		T39	430		T21	19
all_values[15]	auto[1]	auto[0]	auto[1]	30758	1			T21	3		T1	38		T104	2
all_values[15]	auto[1]	auto[1]	auto[1]	30443	1			T21	2		T1	46		T2	44
all_values[16]	auto[0]	auto[0]	auto[0]	2391703	1			T33	357		T34	405		T35	413
all_values[16]	auto[0]	auto[0]	auto[1]	1866414	1			T38	108		T39	427		T21	29
all_values[16]	auto[0]	auto[1]	auto[0]	211514	1			T38	13		T39	69		T21	6
all_values[16]	auto[0]	auto[1]	auto[1]	1870373	1			T38	105		T39	644		T21	8
all_values[16]	auto[1]	auto[0]	auto[1]	30712	1			T21	6		T40	1		T1	44
all_values[16]	auto[1]	auto[1]	auto[1]	30278	1			T21	1		T40	1		T1	43
all_values[17]	auto[0]	auto[0]	auto[0]	2390004	1			T33	357		T34	405		T35	413
all_values[17]	auto[0]	auto[0]	auto[1]	1873588	1			T38	97		T39	486		T21	23
all_values[17]	auto[0]	auto[1]	auto[0]	214035	1			T38	29		T39	114		T21	9
all_values[17]	auto[0]	auto[1]	auto[1]	1862347	1			T38	94		T39	500		T21	24
all_values[17]	auto[1]	auto[0]	auto[1]	30680	1			T21	3		T1	44		T2	34
all_values[17]	auto[1]	auto[1]	auto[1]	30340	1			T21	4		T1	47		T2	30
all_values[18]	auto[0]	auto[0]	auto[0]	2395620	1			T33	357		T34	405		T35	413
all_values[18]	auto[0]	auto[0]	auto[1]	1887621	1			T38	61		T39	387		T21	3
all_values[18]	auto[0]	auto[1]	auto[0]	206066	1			T38	22		T39	96		T21	36
all_values[18]	auto[0]	auto[1]	auto[1]	1850503	1			T38	141		T39	685		T21	19
all_values[18]	auto[1]	auto[0]	auto[1]	30769	1			T21	2		T40	1		T1	42
all_values[18]	auto[1]	auto[1]	auto[1]	30415	1			T21	4		T40	1		T1	47
all_values[19]	auto[0]	auto[0]	auto[0]	2394802	1			T33	357		T34	405		T35	413
all_values[19]	auto[0]	auto[0]	auto[1]	1897584	1			T38	109		T39	448		T21	30
all_values[19]	auto[0]	auto[1]	auto[0]	208891	1			T38	26		T39	38		T30	19
all_values[19]	auto[0]	auto[1]	auto[1]	1838503	1			T38	89		T39	657		T21	18
all_values[19]	auto[1]	auto[0]	auto[1]	31034	1			T21	3		T1	42		T104	1
all_values[19]	auto[1]	auto[1]	auto[1]	30180	1			T21	2		T40	2		T1	44
all_values[20]	auto[0]	auto[0]	auto[0]	2391845	1			T33	357		T34	405		T35	413
all_values[20]	auto[0]	auto[0]	auto[1]	1873240	1			T38	145		T39	551		T21	19
all_values[20]	auto[0]	auto[1]	auto[0]	210087	1			T38	16		T39	60		T21	17
all_values[20]	auto[0]	auto[1]	auto[1]	1864674	1			T38	57		T39	544		T21	17
all_values[20]	auto[1]	auto[0]	auto[1]	30839	1			T21	2		T40	1		T1	38
all_values[20]	auto[1]	auto[1]	auto[1]	30309	1			T21	5		T40	1		T1	45
all_values[21]	auto[0]	auto[0]	auto[0]	2386224	1			T33	357		T34	405		T35	413
all_values[21]	auto[0]	auto[0]	auto[1]	1877014	1			T38	112		T39	549		T21	14
all_values[21]	auto[0]	auto[1]	auto[0]	207885	1			T38	17		T39	89		T21	40
all_values[21]	auto[0]	auto[1]	auto[1]	1868658	1			T38	94		T39	505		T21	5
all_values[21]	auto[1]	auto[0]	auto[1]	31087	1			T21	1		T40	1		T1	61
all_values[21]	auto[1]	auto[1]	auto[1]	30126	1			T21	3		T40	1		T1	30
all_values[22]	auto[0]	auto[0]	auto[0]	2389114	1			T33	357		T34	405		T35	413
all_values[22]	auto[0]	auto[0]	auto[1]	1873157	1			T38	87		T39	614		T21	22
all_values[22]	auto[0]	auto[1]	auto[0]	211815	1			T38	25		T39	39		T21	16
all_values[22]	auto[0]	auto[1]	auto[1]	1866063	1			T38	114		T39	482		T21	6
all_values[22]	auto[1]	auto[0]	auto[1]	30798	1			T21	3		T1	42		T104	1
all_values[22]	auto[1]	auto[1]	auto[1]	30047	1			T21	3		T40	1		T1	45
all_values[23]	auto[0]	auto[0]	auto[0]	2392156	1			T33	357		T34	405		T35	413
all_values[23]	auto[0]	auto[0]	auto[1]	1876627	1			T38	141		T39	546		T21	13
all_values[23]	auto[0]	auto[1]	auto[0]	209042	1			T38	11		T39	50		T21	26
all_values[23]	auto[0]	auto[1]	auto[1]	1861844	1			T38	56		T39	563		T21	14
all_values[23]	auto[1]	auto[0]	auto[1]	31204	1			T21	4		T1	52		T2	39
all_values[23]	auto[1]	auto[1]	auto[1]	30121	1			T21	3		T40	1		T1	40
all_values[24]	auto[0]	auto[0]	auto[0]	2390745	1			T33	357		T34	405		T35	413
all_values[24]	auto[0]	auto[0]	auto[1]	1866135	1			T38	153		T39	559		T21	12
all_values[24]	auto[0]	auto[1]	auto[0]	212015	1			T38	10		T39	90		T21	9
all_values[24]	auto[0]	auto[1]	auto[1]	1871325	1			T38	64		T39	484		T21	12
all_values[24]	auto[1]	auto[0]	auto[1]	30772	1			T21	3		T40	1		T1	39
all_values[24]	auto[1]	auto[1]	auto[1]	30002	1			T21	2		T40	3		T1	49
all_values[25]	auto[0]	auto[0]	auto[0]	2389447	1			T33	357		T34	405		T35	413
all_values[25]	auto[0]	auto[0]	auto[1]	1874678	1			T38	104		T39	621		T21	11
all_values[25]	auto[0]	auto[1]	auto[0]	211899	1			T38	8		T39	45		T21	27
all_values[25]	auto[0]	auto[1]	auto[1]	1863951	1			T38	101		T39	441		T21	16
all_values[25]	auto[1]	auto[0]	auto[1]	30917	1			T21	1		T40	1		T1	58
all_values[25]	auto[1]	auto[1]	auto[1]	30102	1			T21	4		T1	40		T104	1
all_values[26]	auto[0]	auto[0]	auto[0]	2396410	1			T33	357		T34	405		T35	413
all_values[26]	auto[0]	auto[0]	auto[1]	1874969	1			T38	79		T39	488		T21	18
all_values[26]	auto[0]	auto[1]	auto[0]	210629	1			T38	20		T39	42		T21	20
all_values[26]	auto[0]	auto[1]	auto[1]	1857710	1			T38	134		T39	560		T21	21
all_values[26]	auto[1]	auto[0]	auto[1]	31073	1			T21	1		T1	40		T104	1
all_values[26]	auto[1]	auto[1]	auto[1]	30203	1			T21	4		T40	2		T1	46
all_values[27]	auto[0]	auto[0]	auto[0]	2391808	1			T33	357		T34	405		T35	413
all_values[27]	auto[0]	auto[0]	auto[1]	1876167	1			T38	85		T39	429		T21	11
all_values[27]	auto[0]	auto[1]	auto[0]	212008	1			T38	30		T39	80		T21	38
all_values[27]	auto[0]	auto[1]	auto[1]	1860249	1			T38	111		T39	637		T21	5
all_values[27]	auto[1]	auto[0]	auto[1]	30282	1			T21	3		T40	1		T1	28
all_values[27]	auto[1]	auto[1]	auto[1]	30480	1			T21	4		T40	1		T1	61
all_values[28]	auto[0]	auto[0]	auto[0]	2387581	1			T33	357		T34	405		T35	413
all_values[28]	auto[0]	auto[0]	auto[1]	1875622	1			T38	105		T39	572		T21	30
all_values[28]	auto[0]	auto[1]	auto[0]	210291	1			T38	38		T39	32		T21	19
all_values[28]	auto[0]	auto[1]	auto[1]	1866319	1			T38	84		T39	517		T21	6
all_values[28]	auto[1]	auto[0]	auto[1]	30797	1			T21	2		T40	2		T1	47
all_values[28]	auto[1]	auto[1]	auto[1]	30384	1			T21	3		T1	31		T2	51
all_values[29]	auto[0]	auto[0]	auto[0]	2389661	1			T33	357		T34	405		T35	413
all_values[29]	auto[0]	auto[0]	auto[1]	1863508	1			T38	123		T39	642		T21	23
all_values[29]	auto[0]	auto[1]	auto[0]	218519	1			T38	14		T39	45		T21	15
all_values[29]	auto[0]	auto[1]	auto[1]	1868178	1			T38	90		T39	480		T21	11
all_values[29]	auto[1]	auto[0]	auto[1]	30708	1			T21	4		T40	1		T1	44
all_values[29]	auto[1]	auto[1]	auto[1]	30420	1			T21	2		T40	1		T1	40
all_values[30]	auto[0]	auto[0]	auto[0]	2390221	1			T33	357		T34	405		T35	413
all_values[30]	auto[0]	auto[0]	auto[1]	1888030	1			T38	89		T39	599		T21	12
all_values[30]	auto[0]	auto[1]	auto[0]	209480	1			T38	19		T39	89		T21	24
all_values[30]	auto[0]	auto[1]	auto[1]	1852164	1			T38	107		T39	410		T21	13
all_values[30]	auto[1]	auto[0]	auto[1]	30969	1			T21	3		T1	54		T104	2
all_values[30]	auto[1]	auto[1]	auto[1]	30130	1			T21	2		T40	3		T1	41
all_values[31]	auto[0]	auto[0]	auto[0]	2392057	1			T33	357		T34	405		T35	413
all_values[31]	auto[0]	auto[0]	auto[1]	1873732	1			T38	49		T39	527		T21	8
all_values[31]	auto[0]	auto[1]	auto[0]	208992	1			T38	18		T39	96		T21	25
all_values[31]	auto[0]	auto[1]	auto[1]	1865068	1			T38	142		T39	490		T21	15
all_values[31]	auto[1]	auto[0]	auto[1]	30781	1			T21	3		T40	2		T1	32
all_values[31]	auto[1]	auto[1]	auto[1]	30364	1			T21	2		T1	46		T2	33

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal