Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[1]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[2]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[3]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[4]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[5]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[6]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[7]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[8]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[9]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[10]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[11]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[12]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[13]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[14]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[15]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[16]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[17]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[18]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[19]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[20]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[21]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[22]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[23]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[24]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[25]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[26]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[27]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[28]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[29]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[30]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[31]	6356048	1			T33	633		T34	665		T35	794

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102474879

1

T33

5800

T34

14855

T35

19256

auto[1]

100918657

1

T33

14456

T34

6425

T35

6152

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168932383

1

T33

11367

T34

13101

T35

17638

auto[1]

34461153

1

T33

8889

T34

8179

T35

7770

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159154635

1

T33

11611

T34

13153

T35

12178

auto[1]

44238901

1

T33

8645

T34

8127

T35

13230

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2219816	1			T33	42		T34	203		T35	182
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2211563	1			T33	206		T34	81		T35	25
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	540322	1			T33	138		T34	125		T35	98
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	437894	1			T34	116		T35	305		T36	65
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	412562	1			T33	125		T35	34		T36	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	533891	1			T33	122		T34	140		T35	150
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2219566	1			T33	35		T34	215		T35	259
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2211654	1			T33	185		T34	85		T35	31
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	541071	1			T33	118		T34	117		T35	99
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	436099	1			T34	120		T35	250		T36	53
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	412012	1			T33	153		T35	41		T36	25
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	535646	1			T33	142		T34	128		T35	114
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2227795	1			T33	34		T34	178		T35	262
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2204272	1			T33	182		T34	72		T35	33
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	541929	1			T33	110		T34	116		T35	108
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	434877	1			T34	163		T35	203		T36	66
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	412176	1			T33	180		T35	36		T36	24
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	534999	1			T33	127		T34	136		T35	152
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2229038	1			T33	35		T34	222		T35	321
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2203159	1			T33	153		T34	68		T35	33
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	539984	1			T33	134		T34	116		T35	121
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	436024	1			T34	150		T35	227		T36	49
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	411348	1			T33	156		T35	26		T36	9
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	536495	1			T33	155		T34	109		T35	66
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2225705	1			T33	45		T34	169		T35	223
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2209395	1			T33	171		T34	81		T35	20
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	543631	1			T33	122		T34	148		T35	92
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	431634	1			T34	138		T35	267		T36	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	408793	1			T33	137		T35	26		T36	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	536890	1			T33	158		T34	129		T35	166
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2227567	1			T33	44		T34	205		T35	298
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2204340	1			T33	194		T34	65		T35	40
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	544363	1			T33	152		T34	136		T35	111
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	434374	1			T34	106		T35	207		T36	85
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	410858	1			T33	114		T35	14		T36	20
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	534546	1			T33	129		T34	153		T35	124
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2232773	1			T33	38		T34	190		T35	197
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2200262	1			T33	172		T34	74		T35	18
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	542780	1			T33	128		T34	114		T35	70
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	432666	1			T34	156		T35	312		T36	85
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	410053	1			T33	150		T35	49		T36	24
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	537514	1			T33	145		T34	131		T35	148
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2227488	1			T33	35		T34	213		T35	173
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2202597	1			T33	187		T34	73		T35	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	545895	1			T33	139		T34	160		T35	123
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	432270	1			T34	122		T35	273		T36	38
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	408199	1			T33	146		T35	53		T36	11
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	539599	1			T33	126		T34	97		T35	143
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2219664	1			T33	30		T34	190		T35	313
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2206298	1			T33	223		T34	82		T35	44
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	538613	1			T33	104		T34	146		T35	116
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	437529	1			T34	93		T35	230		T36	62
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	412586	1			T33	144		T35	18		T36	27
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	541358	1			T33	132		T34	154		T35	73
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2222119	1			T33	43		T34	207		T35	193
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2206704	1			T33	198		T34	88		T35	25
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	540504	1			T33	108		T34	146		T35	107
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	433990	1			T34	102		T35	234		T36	74
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	413000	1			T33	144		T35	51		T36	27
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	539731	1			T33	140		T34	122		T35	184
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2221352	1			T33	45		T34	216		T35	250
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2211340	1			T33	163		T34	80		T35	36
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	542039	1			T33	110		T34	97		T35	123
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	433775	1			T34	160		T35	248		T36	59
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	410614	1			T33	157		T35	23		T36	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	536928	1			T33	158		T34	112		T35	114
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2242989	1			T33	39		T34	197		T35	185
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2190922	1			T33	205		T34	74		T35	18
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	541338	1			T33	158		T34	98		T35	126
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	435069	1			T34	162		T35	301		T36	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	413755	1			T33	104		T35	49		T36	4
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	531975	1			T33	127		T34	134		T35	115
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2229352	1			T33	39		T34	218		T35	179
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2200861	1			T33	167		T34	70		T35	22
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	540497	1			T33	135		T34	146		T35	93
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	434756	1			T34	100		T35	264		T36	40
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	413405	1			T33	158		T35	49		T36	15
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	537177	1			T33	134		T34	131		T35	187
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2231484	1			T33	33		T34	232		T35	216
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2199523	1			T33	181		T34	67		T35	41
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	539466	1			T33	124		T34	114		T35	137
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	437183	1			T34	134		T35	214		T36	75
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	411510	1			T33	147		T35	32		T36	28
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	536882	1			T33	148		T34	118		T35	154
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2228120	1			T33	39		T34	233		T35	244
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2200801	1			T33	188		T34	73		T35	18
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	542158	1			T33	142		T34	128		T35	106
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	432564	1			T34	115		T35	268		T36	47
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	413728	1			T33	126		T35	46		T36	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	538677	1			T33	138		T34	116		T35	112
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2219872	1			T33	37		T34	228		T35	197
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2212072	1			T33	190		T34	68		T35	32
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	538683	1			T33	162		T34	130		T35	176
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	435290	1			T34	121		T35	267		T36	41
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	412039	1			T33	118		T35	37		T36	5
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	538092	1			T33	126		T34	118		T35	85
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2236012	1			T33	38		T34	161		T35	280
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2200392	1			T33	178		T34	83		T35	42
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	539882	1			T33	122		T34	130		T35	150
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	432923	1			T34	121		T35	177		T36	79
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	413769	1			T33	144		T35	30		T36	23
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	533070	1			T33	151		T34	170		T35	115
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2219577	1			T33	45		T34	197		T35	245
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2211599	1			T33	148		T34	59		T35	32
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	540239	1			T33	168		T34	121		T35	105
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	435373	1			T34	164		T35	244		T36	92
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	412044	1			T33	112		T35	20		T36	22
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	537216	1			T33	160		T34	124		T35	148
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2227657	1			T33	37		T34	211		T35	289
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2200753	1			T33	189		T34	81		T35	35
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	541247	1			T33	159		T34	138		T35	133
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	435549	1			T34	133		T35	215		T36	77
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	413635	1			T33	126		T35	30		T36	22
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	537207	1			T33	122		T34	102		T35	92
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2218619	1			T33	36		T34	208		T35	229
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2216979	1			T33	185		T34	70		T35	32
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	541172	1			T33	140		T34	163		T35	143
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	435157	1			T34	118		T35	209		T36	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	410715	1			T33	116		T35	37		T37	21
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	533406	1			T33	156		T34	106		T35	144
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2224591	1			T33	41		T34	212		T35	297
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2208600	1			T33	139		T34	70		T35	25
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	543026	1			T33	173		T34	151		T35	120
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	434041	1			T34	114		T35	221		T36	86
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	409172	1			T33	100		T35	36		T36	25
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	536618	1			T33	180		T34	118		T35	95
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2227926	1			T33	37		T34	236		T35	177
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2205580	1			T33	209		T34	76		T35	18
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	540934	1			T33	156		T34	106		T35	80
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	435173	1			T34	149		T35	301		T36	46
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	411421	1			T33	131		T35	40		T36	15
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	535014	1			T33	100		T34	98		T35	178
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2230508	1			T33	42		T34	194		T35	215
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2209421	1			T33	156		T34	82		T35	27
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	537287	1			T33	176		T34	114		T35	96
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	432484	1			T34	137		T35	291		T36	17
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	413713	1			T33	139		T35	37		T36	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	532635	1			T33	120		T34	138		T35	128
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2219882	1			T33	40		T34	211		T35	234
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2211143	1			T33	176		T34	76		T35	31
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	538348	1			T33	170		T34	134		T35	130
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	436648	1			T34	118		T35	234		T36	20
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	413733	1			T33	129		T35	24		T36	5
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	536294	1			T33	118		T34	126		T35	141
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2228109	1			T33	41		T34	214		T35	176
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2206267	1			T33	167		T34	74		T35	39
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	542831	1			T33	126		T34	133		T35	124
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	436840	1			T34	112		T35	342		T36	37
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	411225	1			T33	148		T35	27		T36	16
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	530776	1			T33	151		T34	132		T35	86
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2237195	1			T33	42		T34	211		T35	226
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2198667	1			T33	198		T34	63		T35	39
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	543140	1			T33	130		T34	164		T35	106
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	433302	1			T34	86		T35	275		T36	57
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	409959	1			T33	125		T35	43		T36	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	533785	1			T33	138		T34	141		T35	105
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2224361	1			T33	43		T34	182		T35	250
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2208943	1			T33	195		T34	75		T35	40
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	543474	1			T33	143		T34	144		T35	112
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	434745	1			T34	144		T35	235		T36	52
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	411107	1			T33	142		T35	24		T36	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	533418	1			T33	110		T34	120		T35	133
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2226495	1			T33	43		T34	203		T35	276
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2206508	1			T33	162		T34	73		T35	30
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	538660	1			T33	160		T34	134		T35	122
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	434400	1			T34	137		T35	207		T36	47
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	416009	1			T33	144		T35	33		T36	10
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	533976	1			T33	124		T34	118		T35	126
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2225343	1			T33	42		T34	222		T35	258
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2207810	1			T33	196		T34	82		T35	29
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	542812	1			T33	148		T34	102		T35	87
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	432855	1			T34	129		T35	298		T36	79
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	413167	1			T33	119		T35	32		T36	18
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	534061	1			T33	128		T34	130		T35	90
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2221815	1			T33	39		T34	216		T35	260
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2210621	1			T33	190		T34	77		T35	39
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	542069	1			T33	172		T34	136		T35	110
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	433910	1			T34	128		T35	209		T36	56
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	411262	1			T33	112		T35	29		T36	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	536371	1			T33	120		T34	108		T35	147
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2226219	1			T33	35		T34	229		T35	181
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2203853	1			T33	181		T34	73		T35	30
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	541310	1			T33	170		T34	119		T35	136
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	437193	1			T34	122		T35	280		T36	102
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	413511	1			T33	136		T35	33		T36	21
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	533962	1			T33	111		T34	122		T35	134
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2221457	1			T33	45		T34	184		T35	206
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2211181	1			T33	177		T34	81		T35	36
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	540385	1			T33	144		T34	124		T35	138
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	437737	1			T34	128		T35	259		T36	23
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	412433	1			T33	115		T35	32		T36	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	532855	1			T33	152		T34	148		T35	123

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal