Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[1]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[2]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[3]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[4]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[5]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[6]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[7]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[8]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[9]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[10]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[11]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[12]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[13]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[14]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[15]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[16]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[17]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[18]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[19]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[20]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[21]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[22]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[23]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[24]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[25]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[26]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[27]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[28]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[29]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[30]	6356048	1			T33	633		T34	665		T35	794
bins_for_gpio_bits[31]	6356048	1			T33	633		T34	665		T35	794

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102474879

1

T33

5800

T34

14855

T35

19256

auto[1]

100918657

1

T33

14456

T34

6425

T35

6152

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102468703

1

T33

5805

T34

14848

T35

19247

auto[1]

100924833

1

T33

14451

T34

6432

T35

6161

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3101064	1			T33	143		T34	411		T35	560
bins_for_gpio_bits[0]	auto[0]	auto[1]	96778	1			T33	37		T34	33		T35	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	96968	1			T33	37		T34	33		T35	25
bins_for_gpio_bits[0]	auto[1]	auto[1]	3061238	1			T33	416		T34	188		T35	184
bins_for_gpio_bits[1]	auto[0]	auto[0]	3099879	1			T33	116		T34	424		T35	587
bins_for_gpio_bits[1]	auto[0]	auto[1]	96671	1			T33	37		T34	28		T35	21
bins_for_gpio_bits[1]	auto[1]	auto[0]	96857	1			T33	37		T34	28		T35	21
bins_for_gpio_bits[1]	auto[1]	auto[1]	3062641	1			T33	443		T34	185		T35	165
bins_for_gpio_bits[2]	auto[0]	auto[0]	3107571	1			T33	110		T34	424		T35	550
bins_for_gpio_bits[2]	auto[0]	auto[1]	96805	1			T33	34		T34	33		T35	23
bins_for_gpio_bits[2]	auto[1]	auto[0]	97030	1			T33	34		T34	33		T35	23
bins_for_gpio_bits[2]	auto[1]	auto[1]	3054642	1			T33	455		T34	175		T35	198
bins_for_gpio_bits[3]	auto[0]	auto[0]	3108084	1			T33	134		T34	461		T35	655
bins_for_gpio_bits[3]	auto[0]	auto[1]	96746	1			T33	35		T34	26		T35	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	96962	1			T33	35		T34	27		T35	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	3054256	1			T33	429		T34	151		T35	111
bins_for_gpio_bits[4]	auto[0]	auto[0]	3103969	1			T33	137		T34	414		T35	558
bins_for_gpio_bits[4]	auto[0]	auto[1]	96825	1			T33	30		T34	40		T35	24
bins_for_gpio_bits[4]	auto[1]	auto[0]	97001	1			T33	30		T34	41		T35	24
bins_for_gpio_bits[4]	auto[1]	auto[1]	3058253	1			T33	436		T34	170		T35	188
bins_for_gpio_bits[5]	auto[0]	auto[0]	3109014	1			T33	158		T34	408		T35	597
bins_for_gpio_bits[5]	auto[0]	auto[1]	97097	1			T33	38		T34	38		T35	19
bins_for_gpio_bits[5]	auto[1]	auto[0]	97290	1			T33	38		T34	39		T35	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	3052647	1			T33	399		T34	180		T35	159
bins_for_gpio_bits[6]	auto[0]	auto[0]	3111238	1			T33	131		T34	429		T35	558
bins_for_gpio_bits[6]	auto[0]	auto[1]	96784	1			T33	35		T34	30		T35	20
bins_for_gpio_bits[6]	auto[1]	auto[0]	96981	1			T33	35		T34	31		T35	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	3051045	1			T33	432		T34	175		T35	195
bins_for_gpio_bits[7]	auto[0]	auto[0]	3108388	1			T33	138		T34	459		T35	544
bins_for_gpio_bits[7]	auto[0]	auto[1]	97090	1			T33	37		T34	35		T35	25
bins_for_gpio_bits[7]	auto[1]	auto[0]	97265	1			T33	36		T34	36		T35	25
bins_for_gpio_bits[7]	auto[1]	auto[1]	3053305	1			T33	422		T34	135		T35	200
bins_for_gpio_bits[8]	auto[0]	auto[0]	3099129	1			T33	101		T34	398		T35	645
bins_for_gpio_bits[8]	auto[0]	auto[1]	96481	1			T33	33		T34	31		T35	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	96677	1			T33	33		T34	31		T35	14
bins_for_gpio_bits[8]	auto[1]	auto[1]	3063761	1			T33	466		T34	205		T35	121
bins_for_gpio_bits[9]	auto[0]	auto[0]	3099722	1			T33	121		T34	418		T35	509
bins_for_gpio_bits[9]	auto[0]	auto[1]	96691	1			T33	30		T34	37		T35	25
bins_for_gpio_bits[9]	auto[1]	auto[0]	96891	1			T33	30		T34	37		T35	25
bins_for_gpio_bits[9]	auto[1]	auto[1]	3062744	1			T33	452		T34	173		T35	235
bins_for_gpio_bits[10]	auto[0]	auto[0]	3099899	1			T33	121		T34	442		T35	597
bins_for_gpio_bits[10]	auto[0]	auto[1]	97054	1			T33	34		T34	31		T35	23
bins_for_gpio_bits[10]	auto[1]	auto[0]	97267	1			T33	34		T34	31		T35	24
bins_for_gpio_bits[10]	auto[1]	auto[1]	3061828	1			T33	444		T34	161		T35	150
bins_for_gpio_bits[11]	auto[0]	auto[0]	3122810	1			T33	161		T34	426		T35	588
bins_for_gpio_bits[11]	auto[0]	auto[1]	96390	1			T33	36		T34	31		T35	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	96586	1			T33	36		T34	31		T35	24
bins_for_gpio_bits[11]	auto[1]	auto[1]	3040262	1			T33	400		T34	177		T35	158
bins_for_gpio_bits[12]	auto[0]	auto[0]	3107578	1			T33	142		T34	432		T35	508
bins_for_gpio_bits[12]	auto[0]	auto[1]	96819	1			T33	33		T34	31		T35	28
bins_for_gpio_bits[12]	auto[1]	auto[0]	97027	1			T33	32		T34	32		T35	28
bins_for_gpio_bits[12]	auto[1]	auto[1]	3054624	1			T33	426		T34	170		T35	230
bins_for_gpio_bits[13]	auto[0]	auto[0]	3111067	1			T33	120		T34	449		T35	545
bins_for_gpio_bits[13]	auto[0]	auto[1]	96865	1			T33	37		T34	31		T35	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	97066	1			T33	37		T34	31		T35	22
bins_for_gpio_bits[13]	auto[1]	auto[1]	3051050	1			T33	439		T34	154		T35	205
bins_for_gpio_bits[14]	auto[0]	auto[0]	3106242	1			T33	151		T34	444		T35	598
bins_for_gpio_bits[14]	auto[0]	auto[1]	96396	1			T33	30		T34	32		T35	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	96600	1			T33	30		T34	32		T35	20
bins_for_gpio_bits[14]	auto[1]	auto[1]	3056810	1			T33	422		T34	157		T35	157
bins_for_gpio_bits[15]	auto[0]	auto[0]	3097014	1			T33	169		T34	449		T35	621
bins_for_gpio_bits[15]	auto[0]	auto[1]	96655	1			T33	30		T34	30		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[0]	96831	1			T33	30		T34	30		T35	19
bins_for_gpio_bits[15]	auto[1]	auto[1]	3065548	1			T33	404		T34	156		T35	135
bins_for_gpio_bits[16]	auto[0]	auto[0]	3112018	1			T33	127		T34	376		T35	592
bins_for_gpio_bits[16]	auto[0]	auto[1]	96567	1			T33	33		T34	36		T35	15
bins_for_gpio_bits[16]	auto[1]	auto[0]	96799	1			T33	33		T34	36		T35	15
bins_for_gpio_bits[16]	auto[1]	auto[1]	3050664	1			T33	440		T34	217		T35	172
bins_for_gpio_bits[17]	auto[0]	auto[0]	3097958	1			T33	183		T34	451		T35	569
bins_for_gpio_bits[17]	auto[0]	auto[1]	97055	1			T33	30		T34	31		T35	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	97231	1			T33	30		T34	31		T35	25
bins_for_gpio_bits[17]	auto[1]	auto[1]	3063804	1			T33	390		T34	152		T35	175
bins_for_gpio_bits[18]	auto[0]	auto[0]	3107219	1			T33	161		T34	450		T35	620
bins_for_gpio_bits[18]	auto[0]	auto[1]	97055	1			T33	36		T34	32		T35	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	97234	1			T33	35		T34	32		T35	17
bins_for_gpio_bits[18]	auto[1]	auto[1]	3054540	1			T33	401		T34	151		T35	140
bins_for_gpio_bits[19]	auto[0]	auto[0]	3097946	1			T33	142		T34	455		T35	556
bins_for_gpio_bits[19]	auto[0]	auto[1]	96875	1			T33	34		T34	34		T35	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	97002	1			T33	34		T34	34		T35	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	3064225	1			T33	423		T34	142		T35	189
bins_for_gpio_bits[20]	auto[0]	auto[0]	3104149	1			T33	173		T34	446		T35	621
bins_for_gpio_bits[20]	auto[0]	auto[1]	97313	1			T33	42		T34	31		T35	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	97509	1			T33	41		T34	31		T35	17
bins_for_gpio_bits[20]	auto[1]	auto[1]	3057077	1			T33	377		T34	157		T35	139
bins_for_gpio_bits[21]	auto[0]	auto[0]	3107318	1			T33	158		T34	464		T35	531
bins_for_gpio_bits[21]	auto[0]	auto[1]	96559	1			T33	35		T34	27		T35	27
bins_for_gpio_bits[21]	auto[1]	auto[0]	96715	1			T33	35		T34	27		T35	27
bins_for_gpio_bits[21]	auto[1]	auto[1]	3055456	1			T33	405		T34	147		T35	209
bins_for_gpio_bits[22]	auto[0]	auto[0]	3103682	1			T33	179		T34	411		T35	583
bins_for_gpio_bits[22]	auto[0]	auto[1]	96381	1			T33	39		T34	34		T35	19
bins_for_gpio_bits[22]	auto[1]	auto[0]	96597	1			T33	39		T34	34		T35	19
bins_for_gpio_bits[22]	auto[1]	auto[1]	3059388	1			T33	376		T34	186		T35	173
bins_for_gpio_bits[23]	auto[0]	auto[0]	3097702	1			T33	175		T34	432		T35	577
bins_for_gpio_bits[23]	auto[0]	auto[1]	96971	1			T33	35		T34	31		T35	20
bins_for_gpio_bits[23]	auto[1]	auto[0]	97176	1			T33	35		T34	31		T35	21
bins_for_gpio_bits[23]	auto[1]	auto[1]	3064199	1			T33	388		T34	171		T35	176
bins_for_gpio_bits[24]	auto[0]	auto[0]	3110390	1			T33	141		T34	429		T35	620
bins_for_gpio_bits[24]	auto[0]	auto[1]	97230	1			T33	26		T34	30		T35	22
bins_for_gpio_bits[24]	auto[1]	auto[0]	97390	1			T33	26		T34	30		T35	22
bins_for_gpio_bits[24]	auto[1]	auto[1]	3051038	1			T33	440		T34	176		T35	130
bins_for_gpio_bits[25]	auto[0]	auto[0]	3116698	1			T33	136		T34	429		T35	580
bins_for_gpio_bits[25]	auto[0]	auto[1]	96702	1			T33	36		T34	31		T35	27
bins_for_gpio_bits[25]	auto[1]	auto[0]	96939	1			T33	36		T34	32		T35	27
bins_for_gpio_bits[25]	auto[1]	auto[1]	3045709	1			T33	425		T34	173		T35	160
bins_for_gpio_bits[26]	auto[0]	auto[0]	3105455	1			T33	155		T34	438		T35	574
bins_for_gpio_bits[26]	auto[0]	auto[1]	96906	1			T33	32		T34	32		T35	22
bins_for_gpio_bits[26]	auto[1]	auto[0]	97125	1			T33	31		T34	32		T35	23
bins_for_gpio_bits[26]	auto[1]	auto[1]	3056562	1			T33	415		T34	163		T35	175
bins_for_gpio_bits[27]	auto[0]	auto[0]	3102971	1			T33	169		T34	445		T35	583
bins_for_gpio_bits[27]	auto[0]	auto[1]	96417	1			T33	34		T34	29		T35	21
bins_for_gpio_bits[27]	auto[1]	auto[0]	96584	1			T33	34		T34	29		T35	22
bins_for_gpio_bits[27]	auto[1]	auto[1]	3060076	1			T33	396		T34	162		T35	168
bins_for_gpio_bits[28]	auto[0]	auto[0]	3104348	1			T33	154		T34	423		T35	626
bins_for_gpio_bits[28]	auto[0]	auto[1]	96509	1			T33	36		T34	30		T35	17
bins_for_gpio_bits[28]	auto[1]	auto[0]	96662	1			T33	36		T34	30		T35	17
bins_for_gpio_bits[28]	auto[1]	auto[1]	3058529	1			T33	407		T34	182		T35	134
bins_for_gpio_bits[29]	auto[0]	auto[0]	3100694	1			T33	174		T34	452		T35	555
bins_for_gpio_bits[29]	auto[0]	auto[1]	96903	1			T33	37		T34	28		T35	23
bins_for_gpio_bits[29]	auto[1]	auto[0]	97100	1			T33	37		T34	28		T35	24
bins_for_gpio_bits[29]	auto[1]	auto[1]	3061351	1			T33	385		T34	157		T35	192
bins_for_gpio_bits[30]	auto[0]	auto[0]	3107589	1			T33	168		T34	441		T35	572
bins_for_gpio_bits[30]	auto[0]	auto[1]	96936	1			T33	37		T34	29		T35	25
bins_for_gpio_bits[30]	auto[1]	auto[0]	97133	1			T33	37		T34	29		T35	25
bins_for_gpio_bits[30]	auto[1]	auto[1]	3054390	1			T33	391		T34	166		T35	172
bins_for_gpio_bits[31]	auto[0]	auto[0]	3102441	1			T33	155		T34	405		T35	581
bins_for_gpio_bits[31]	auto[0]	auto[1]	96931	1			T33	34		T34	31		T35	21
bins_for_gpio_bits[31]	auto[1]	auto[0]	97138	1			T33	34		T34	31		T35	22
bins_for_gpio_bits[31]	auto[1]	auto[1]	3059538	1			T33	410		T34	198		T35	170