Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4297309 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2103685 |
1 |
|
|
T38 |
100 |
|
T39 |
431 |
|
T21 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6136258 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
264736 |
1 |
|
|
T38 |
12 |
|
T39 |
109 |
|
T30 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4285893 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2115101 |
1 |
|
|
T38 |
133 |
|
T39 |
634 |
|
T21 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
930189 |
1 |
|
|
T38 |
71 |
|
T39 |
373 |
|
T21 |
12 |
| auto[1] |
auto[0] |
auto[1] |
132620 |
1 |
|
|
T38 |
8 |
|
T39 |
81 |
|
T30 |
2 |
| auto[1] |
auto[1] |
auto[0] |
920176 |
1 |
|
|
T38 |
50 |
|
T39 |
152 |
|
T21 |
11 |
| auto[1] |
auto[1] |
auto[1] |
132116 |
1 |
|
|
T38 |
4 |
|
T39 |
28 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |