Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4289703 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2111291 |
1 |
|
|
T38 |
131 |
|
T39 |
747 |
|
T21 |
19 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6140298 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
260696 |
1 |
|
|
T38 |
8 |
|
T39 |
131 |
|
T21 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305392 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2095602 |
1 |
|
|
T38 |
115 |
|
T39 |
756 |
|
T21 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
917983 |
1 |
|
|
T38 |
48 |
|
T39 |
263 |
|
T21 |
31 |
| auto[1] |
auto[0] |
auto[1] |
130239 |
1 |
|
|
T38 |
4 |
|
T39 |
57 |
|
T21 |
1 |
| auto[1] |
auto[1] |
auto[0] |
916923 |
1 |
|
|
T38 |
59 |
|
T39 |
362 |
|
T21 |
12 |
| auto[1] |
auto[1] |
auto[1] |
130457 |
1 |
|
|
T38 |
4 |
|
T39 |
74 |
|
T57 |
72 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |