Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4298257 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2102737 |
1 |
|
|
T38 |
141 |
|
T39 |
717 |
|
T21 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6138773 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
262221 |
1 |
|
|
T38 |
8 |
|
T39 |
106 |
|
T30 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4298640 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2102354 |
1 |
|
|
T38 |
145 |
|
T39 |
550 |
|
T21 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
924348 |
1 |
|
|
T38 |
67 |
|
T39 |
130 |
|
T21 |
17 |
| auto[1] |
auto[0] |
auto[1] |
132217 |
1 |
|
|
T38 |
4 |
|
T39 |
30 |
|
T30 |
4 |
| auto[1] |
auto[1] |
auto[0] |
915785 |
1 |
|
|
T38 |
70 |
|
T39 |
314 |
|
T21 |
14 |
| auto[1] |
auto[1] |
auto[1] |
130004 |
1 |
|
|
T38 |
4 |
|
T39 |
76 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |