Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4283877 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2117117 |
1 |
|
|
T38 |
104 |
|
T39 |
525 |
|
T21 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6135915 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
265079 |
1 |
|
|
T38 |
13 |
|
T39 |
98 |
|
T30 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4285735 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
| auto[1] |
2115259 |
1 |
|
|
T38 |
127 |
|
T39 |
547 |
|
T21 |
29 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
919936 |
1 |
|
|
T38 |
71 |
|
T39 |
222 |
|
T21 |
29 |
| auto[1] |
auto[0] |
auto[1] |
131410 |
1 |
|
|
T38 |
9 |
|
T39 |
48 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
930244 |
1 |
|
|
T38 |
43 |
|
T39 |
227 |
|
T30 |
62 |
| auto[1] |
auto[1] |
auto[1] |
133669 |
1 |
|
|
T38 |
4 |
|
T39 |
50 |
|
T30 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |