Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4289703 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2111291 |
1 |
|
|
T38 |
131 |
|
T39 |
747 |
|
T21 |
19 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5356021 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1044973 |
1 |
|
|
T38 |
32 |
|
T39 |
291 |
|
T21 |
5 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4300969 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2100025 |
1 |
|
|
T38 |
54 |
|
T39 |
585 |
|
T21 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
528527 |
1 |
|
|
T38 |
5 |
|
T39 |
44 |
|
T21 |
28 |
auto[1] |
auto[0] |
auto[1] |
520812 |
1 |
|
|
T38 |
18 |
|
T39 |
51 |
|
T21 |
2 |
auto[1] |
auto[1] |
auto[0] |
526525 |
1 |
|
|
T38 |
17 |
|
T39 |
250 |
|
T21 |
6 |
auto[1] |
auto[1] |
auto[1] |
524161 |
1 |
|
|
T38 |
14 |
|
T39 |
240 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4296556 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2104438 |
1 |
|
|
T38 |
98 |
|
T39 |
462 |
|
T21 |
29 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5343194 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1057800 |
1 |
|
|
T38 |
40 |
|
T39 |
372 |
|
T21 |
41 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4307124 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2093870 |
1 |
|
|
T38 |
116 |
|
T39 |
768 |
|
T21 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
519231 |
1 |
|
|
T38 |
55 |
|
T39 |
261 |
|
T21 |
2 |
auto[1] |
auto[0] |
auto[1] |
528988 |
1 |
|
|
T38 |
20 |
|
T39 |
237 |
|
T21 |
30 |
auto[1] |
auto[1] |
auto[0] |
516839 |
1 |
|
|
T38 |
21 |
|
T39 |
135 |
|
T21 |
6 |
auto[1] |
auto[1] |
auto[1] |
528812 |
1 |
|
|
T38 |
20 |
|
T39 |
135 |
|
T21 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4293567 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2107427 |
1 |
|
|
T38 |
100 |
|
T39 |
573 |
|
T21 |
29 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5338137 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1062857 |
1 |
|
|
T38 |
93 |
|
T39 |
294 |
|
T21 |
6 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4288983 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2112011 |
1 |
|
|
T38 |
164 |
|
T39 |
624 |
|
T21 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
525181 |
1 |
|
|
T38 |
43 |
|
T39 |
159 |
|
T21 |
2 |
auto[1] |
auto[0] |
auto[1] |
534120 |
1 |
|
|
T38 |
47 |
|
T39 |
160 |
|
T21 |
6 |
auto[1] |
auto[1] |
auto[0] |
523973 |
1 |
|
|
T38 |
28 |
|
T39 |
171 |
|
T21 |
2 |
auto[1] |
auto[1] |
auto[1] |
528737 |
1 |
|
|
T38 |
46 |
|
T39 |
134 |
|
T30 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4296659 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2104335 |
1 |
|
|
T38 |
161 |
|
T39 |
518 |
|
T21 |
18 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5346294 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1054700 |
1 |
|
|
T38 |
124 |
|
T39 |
301 |
|
T21 |
12 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4300732 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2100262 |
1 |
|
|
T38 |
178 |
|
T39 |
585 |
|
T21 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
525279 |
1 |
|
|
T38 |
8 |
|
T39 |
185 |
|
T21 |
4 |
auto[1] |
auto[0] |
auto[1] |
532658 |
1 |
|
|
T38 |
48 |
|
T39 |
178 |
|
T21 |
9 |
auto[1] |
auto[1] |
auto[0] |
520283 |
1 |
|
|
T38 |
46 |
|
T39 |
99 |
|
T21 |
4 |
auto[1] |
auto[1] |
auto[1] |
522042 |
1 |
|
|
T38 |
76 |
|
T39 |
123 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4278975 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2122019 |
1 |
|
|
T38 |
139 |
|
T39 |
605 |
|
T21 |
28 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5349164 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1051830 |
1 |
|
|
T38 |
23 |
|
T39 |
336 |
|
T30 |
32 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4306940 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2094054 |
1 |
|
|
T38 |
48 |
|
T39 |
672 |
|
T21 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
516613 |
1 |
|
|
T38 |
4 |
|
T39 |
195 |
|
T21 |
2 |
auto[1] |
auto[0] |
auto[1] |
520088 |
1 |
|
|
T38 |
7 |
|
T39 |
198 |
|
T30 |
13 |
auto[1] |
auto[1] |
auto[0] |
525611 |
1 |
|
|
T38 |
21 |
|
T39 |
141 |
|
T30 |
19 |
auto[1] |
auto[1] |
auto[1] |
531742 |
1 |
|
|
T38 |
16 |
|
T39 |
138 |
|
T30 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4303136 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2097858 |
1 |
|
|
T38 |
104 |
|
T39 |
559 |
|
T21 |
34 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5344451 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1056543 |
1 |
|
|
T38 |
92 |
|
T39 |
378 |
|
T21 |
17 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4297238 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2103756 |
1 |
|
|
T38 |
148 |
|
T39 |
750 |
|
T21 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
530754 |
1 |
|
|
T38 |
23 |
|
T39 |
206 |
|
T21 |
12 |
auto[1] |
auto[0] |
auto[1] |
535615 |
1 |
|
|
T38 |
57 |
|
T39 |
230 |
|
T21 |
10 |
auto[1] |
auto[1] |
auto[0] |
516459 |
1 |
|
|
T38 |
33 |
|
T39 |
166 |
|
T21 |
2 |
auto[1] |
auto[1] |
auto[1] |
520928 |
1 |
|
|
T38 |
35 |
|
T39 |
148 |
|
T21 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4300644 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2100350 |
1 |
|
|
T38 |
109 |
|
T39 |
572 |
|
T21 |
15 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5339785 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1061209 |
1 |
|
|
T38 |
57 |
|
T39 |
356 |
|
T21 |
19 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4296050 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2104944 |
1 |
|
|
T38 |
128 |
|
T39 |
706 |
|
T21 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
527495 |
1 |
|
|
T38 |
33 |
|
T39 |
160 |
|
T21 |
9 |
auto[1] |
auto[0] |
auto[1] |
533926 |
1 |
|
|
T38 |
35 |
|
T39 |
197 |
|
T21 |
8 |
auto[1] |
auto[1] |
auto[0] |
516240 |
1 |
|
|
T38 |
38 |
|
T39 |
190 |
|
T30 |
16 |
auto[1] |
auto[1] |
auto[1] |
527283 |
1 |
|
|
T38 |
22 |
|
T39 |
159 |
|
T21 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4298515 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2102479 |
1 |
|
|
T38 |
155 |
|
T39 |
564 |
|
T21 |
41 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5334281 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1066713 |
1 |
|
|
T38 |
37 |
|
T39 |
219 |
|
T30 |
24 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4287142 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2113852 |
1 |
|
|
T38 |
86 |
|
T39 |
418 |
|
T21 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
524165 |
1 |
|
|
T38 |
9 |
|
T39 |
130 |
|
T21 |
2 |
auto[1] |
auto[0] |
auto[1] |
532112 |
1 |
|
|
T38 |
9 |
|
T39 |
134 |
|
T30 |
23 |
auto[1] |
auto[1] |
auto[0] |
522974 |
1 |
|
|
T38 |
40 |
|
T39 |
69 |
|
T21 |
4 |
auto[1] |
auto[1] |
auto[1] |
534601 |
1 |
|
|
T38 |
28 |
|
T39 |
85 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4302352 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2098642 |
1 |
|
|
T38 |
123 |
|
T39 |
456 |
|
T21 |
33 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5346777 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1054217 |
1 |
|
|
T38 |
52 |
|
T39 |
233 |
|
T21 |
10 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4300749 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2100245 |
1 |
|
|
T38 |
91 |
|
T39 |
505 |
|
T21 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
526418 |
1 |
|
|
T38 |
24 |
|
T39 |
130 |
|
T21 |
3 |
auto[1] |
auto[0] |
auto[1] |
531280 |
1 |
|
|
T38 |
20 |
|
T39 |
115 |
|
T21 |
7 |
auto[1] |
auto[1] |
auto[0] |
519610 |
1 |
|
|
T38 |
15 |
|
T39 |
142 |
|
T21 |
23 |
auto[1] |
auto[1] |
auto[1] |
522937 |
1 |
|
|
T38 |
32 |
|
T39 |
118 |
|
T21 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4288829 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2112165 |
1 |
|
|
T38 |
118 |
|
T39 |
713 |
|
T21 |
15 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5342745 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1058249 |
1 |
|
|
T38 |
35 |
|
T39 |
292 |
|
T21 |
21 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4296529 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2104465 |
1 |
|
|
T38 |
82 |
|
T39 |
573 |
|
T21 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
520652 |
1 |
|
|
T38 |
23 |
|
T39 |
124 |
|
T21 |
22 |
auto[1] |
auto[0] |
auto[1] |
527240 |
1 |
|
|
T38 |
10 |
|
T39 |
141 |
|
T21 |
15 |
auto[1] |
auto[1] |
auto[0] |
525564 |
1 |
|
|
T38 |
24 |
|
T39 |
157 |
|
T21 |
3 |
auto[1] |
auto[1] |
auto[1] |
531009 |
1 |
|
|
T38 |
25 |
|
T39 |
151 |
|
T21 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4294272 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2106722 |
1 |
|
|
T38 |
123 |
|
T39 |
614 |
|
T21 |
37 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5347908 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1053086 |
1 |
|
|
T38 |
40 |
|
T39 |
199 |
|
T21 |
33 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4302991 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2098003 |
1 |
|
|
T38 |
86 |
|
T39 |
459 |
|
T21 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
523826 |
1 |
|
|
T38 |
19 |
|
T39 |
125 |
|
T30 |
5 |
auto[1] |
auto[0] |
auto[1] |
528457 |
1 |
|
|
T38 |
28 |
|
T39 |
91 |
|
T21 |
14 |
auto[1] |
auto[1] |
auto[0] |
521091 |
1 |
|
|
T38 |
27 |
|
T39 |
135 |
|
T21 |
2 |
auto[1] |
auto[1] |
auto[1] |
524629 |
1 |
|
|
T38 |
12 |
|
T39 |
108 |
|
T21 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4314010 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2086984 |
1 |
|
|
T38 |
163 |
|
T39 |
781 |
|
T21 |
59 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5349733 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1051261 |
1 |
|
|
T38 |
88 |
|
T39 |
307 |
|
T21 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4302427 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2098567 |
1 |
|
|
T38 |
159 |
|
T39 |
656 |
|
T21 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
528845 |
1 |
|
|
T38 |
29 |
|
T39 |
113 |
|
T21 |
2 |
auto[1] |
auto[0] |
auto[1] |
531089 |
1 |
|
|
T38 |
28 |
|
T39 |
95 |
|
T30 |
11 |
auto[1] |
auto[1] |
auto[0] |
518461 |
1 |
|
|
T38 |
42 |
|
T39 |
236 |
|
T21 |
28 |
auto[1] |
auto[1] |
auto[1] |
520172 |
1 |
|
|
T38 |
60 |
|
T39 |
212 |
|
T21 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4323420 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2077574 |
1 |
|
|
T38 |
115 |
|
T39 |
695 |
|
T21 |
20 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
5344983 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
1056011 |
1 |
|
|
T38 |
92 |
|
T39 |
482 |
|
T21 |
13 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4309215 |
1 |
|
|
T33 |
357 |
|
T34 |
405 |
|
T35 |
413 |
auto[1] |
2091779 |
1 |
|
|
T38 |
147 |
|
T39 |
959 |
|
T21 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
524097 |
1 |
|
|
T38 |
22 |
|
T39 |
174 |
|
T21 |
8 |
auto[1] |
auto[0] |
auto[1] |
532511 |
1 |
|
|
T38 |
46 |
|
T39 |
205 |
|
T21 |
6 |
auto[1] |
auto[1] |
auto[0] |
511671 |
1 |
|
|
T38 |
33 |
|
T39 |
303 |
|
T30 |
5 |
auto[1] |
auto[1] |
auto[1] |
523500 |
1 |
|
|
T38 |
46 |
|
T39 |
277 |
|
T21 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |