Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1665623	1			T43	1		T44	1		T45	1
all_pins[1]	1665623	1			T43	1		T44	1		T45	1
all_pins[2]	1665623	1			T43	1		T44	1		T45	1
all_pins[3]	1665623	1			T43	1		T44	1		T45	1
all_pins[4]	1665623	1			T43	1		T44	1		T45	1
all_pins[5]	1665623	1			T43	1		T44	1		T45	1
all_pins[6]	1665623	1			T43	1		T44	1		T45	1
all_pins[7]	1665623	1			T43	1		T44	1		T45	1
all_pins[8]	1665623	1			T43	1		T44	1		T45	1
all_pins[9]	1665623	1			T43	1		T44	1		T45	1
all_pins[10]	1665623	1			T43	1		T44	1		T45	1
all_pins[11]	1665623	1			T43	1		T44	1		T45	1
all_pins[12]	1665623	1			T43	1		T44	1		T45	1
all_pins[13]	1665623	1			T43	1		T44	1		T45	1
all_pins[14]	1665623	1			T43	1		T44	1		T45	1
all_pins[15]	1665623	1			T43	1		T44	1		T45	1
all_pins[16]	1665623	1			T43	1		T44	1		T45	1
all_pins[17]	1665623	1			T43	1		T44	1		T45	1
all_pins[18]	1665623	1			T43	1		T44	1		T45	1
all_pins[19]	1665623	1			T43	1		T44	1		T45	1
all_pins[20]	1665623	1			T43	1		T44	1		T45	1
all_pins[21]	1665623	1			T43	1		T44	1		T45	1
all_pins[22]	1665623	1			T43	1		T44	1		T45	1
all_pins[23]	1665623	1			T43	1		T44	1		T45	1
all_pins[24]	1665623	1			T43	1		T44	1		T45	1
all_pins[25]	1665623	1			T43	1		T44	1		T45	1
all_pins[26]	1665623	1			T43	1		T44	1		T45	1
all_pins[27]	1665623	1			T43	1		T44	1		T45	1
all_pins[28]	1665623	1			T43	1		T44	1		T45	1
all_pins[29]	1665623	1			T43	1		T44	1		T45	1
all_pins[30]	1665623	1			T43	1		T44	1		T45	1
all_pins[31]	1665623	1			T43	1		T44	1		T45	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	33128368	1			T43	32		T44	32		T45	32
values[0x1]	20171568	1			T31	261		T38	2001		T39	3158
transitions[0x0=>0x1]	12068382	1			T31	168		T38	1239		T39	1856
transitions[0x1=>0x0]	12068240	1			T31	167		T38	1239		T39	1856

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1037440	1			T43	1		T44	1		T45	1
all_pins[0]	values[0x1]	628183	1			T31	14		T38	78		T39	110
all_pins[0]	transitions[0x0=>0x1]	389374	1			T31	9		T38	57		T39	63
all_pins[0]	transitions[0x1=>0x0]	390071	1			T31	2		T38	33		T39	91
all_pins[1]	values[0x0]	1035485	1			T43	1		T44	1		T45	1
all_pins[1]	values[0x1]	630138	1			T31	8		T38	55		T39	144
all_pins[1]	transitions[0x0=>0x1]	377218	1			T31	4		T38	42		T39	91
all_pins[1]	transitions[0x1=>0x0]	375263	1			T31	10		T38	65		T39	57
all_pins[2]	values[0x0]	1032920	1			T43	1		T44	1		T45	1
all_pins[2]	values[0x1]	632703	1			T31	12		T38	75		T39	80
all_pins[2]	transitions[0x0=>0x1]	377056	1			T31	7		T38	41		T39	29
all_pins[2]	transitions[0x1=>0x0]	374491	1			T31	3		T38	21		T39	93
all_pins[3]	values[0x0]	1040080	1			T43	1		T44	1		T45	1
all_pins[3]	values[0x1]	625543	1			T31	3		T38	92		T39	61
all_pins[3]	transitions[0x0=>0x1]	371064	1			T38	49		T39	22		T70	20
all_pins[3]	transitions[0x1=>0x0]	378224	1			T31	9		T38	32		T39	41
all_pins[4]	values[0x0]	1036771	1			T43	1		T44	1		T45	1
all_pins[4]	values[0x1]	628852	1			T31	9		T38	45		T39	111
all_pins[4]	transitions[0x0=>0x1]	377528	1			T31	6		T38	16		T39	98
all_pins[4]	transitions[0x1=>0x0]	374219	1			T38	63		T39	48		T70	20
all_pins[5]	values[0x0]	1036533	1			T43	1		T44	1		T45	1
all_pins[5]	values[0x1]	629090	1			T31	10		T38	71		T39	142
all_pins[5]	transitions[0x0=>0x1]	376868	1			T31	10		T38	47		T39	64
all_pins[5]	transitions[0x1=>0x0]	376630	1			T31	9		T38	21		T39	33
all_pins[6]	values[0x0]	1033093	1			T43	1		T44	1		T45	1
all_pins[6]	values[0x1]	632530	1			T31	9		T38	71		T39	76
all_pins[6]	transitions[0x0=>0x1]	378439	1			T31	6		T38	30		T39	41
all_pins[6]	transitions[0x1=>0x0]	374999	1			T31	7		T38	30		T39	107
all_pins[7]	values[0x0]	1037567	1			T43	1		T44	1		T45	1
all_pins[7]	values[0x1]	628056	1			T31	11		T38	81		T39	102
all_pins[7]	transitions[0x0=>0x1]	375591	1			T31	6		T38	47		T39	93
all_pins[7]	transitions[0x1=>0x0]	380065	1			T31	4		T38	37		T39	67
all_pins[8]	values[0x0]	1034224	1			T43	1		T44	1		T45	1
all_pins[8]	values[0x1]	631399	1			T31	10		T38	47		T39	63
all_pins[8]	transitions[0x0=>0x1]	377615	1			T31	3		T38	18		T39	49
all_pins[8]	transitions[0x1=>0x0]	374272	1			T31	4		T38	52		T39	88
all_pins[9]	values[0x0]	1030584	1			T43	1		T44	1		T45	1
all_pins[9]	values[0x1]	635039	1			T31	5		T38	61		T39	35
all_pins[9]	transitions[0x0=>0x1]	378623	1			T31	1		T38	43		T39	24
all_pins[9]	transitions[0x1=>0x0]	374983	1			T31	6		T38	29		T39	52
all_pins[10]	values[0x0]	1037575	1			T43	1		T44	1		T45	1
all_pins[10]	values[0x1]	628048	1			T31	10		T38	41		T39	95
all_pins[10]	transitions[0x0=>0x1]	373902	1			T31	10		T38	22		T39	84
all_pins[10]	transitions[0x1=>0x0]	380893	1			T31	5		T38	42		T39	24
all_pins[11]	values[0x0]	1034173	1			T43	1		T44	1		T45	1
all_pins[11]	values[0x1]	631450	1			T31	7		T38	71		T39	84
all_pins[11]	transitions[0x0=>0x1]	377655	1			T31	2		T38	61		T39	61
all_pins[11]	transitions[0x1=>0x0]	374253	1			T31	5		T38	31		T39	72
all_pins[12]	values[0x0]	1037219	1			T43	1		T44	1		T45	1
all_pins[12]	values[0x1]	628404	1			T31	13		T38	60		T39	91
all_pins[12]	transitions[0x0=>0x1]	375421	1			T31	7		T38	50		T39	63
all_pins[12]	transitions[0x1=>0x0]	378467	1			T31	1		T38	61		T39	56
all_pins[13]	values[0x0]	1036370	1			T43	1		T44	1		T45	1
all_pins[13]	values[0x1]	629253	1			T38	39		T39	122		T70	17
all_pins[13]	transitions[0x0=>0x1]	377315	1			T38	21		T39	47		T70	16
all_pins[13]	transitions[0x1=>0x0]	376466	1			T31	13		T38	42		T39	16
all_pins[14]	values[0x0]	1036677	1			T43	1		T44	1		T45	1
all_pins[14]	values[0x1]	628946	1			T31	2		T38	62		T39	139
all_pins[14]	transitions[0x0=>0x1]	376337	1			T31	2		T38	47		T39	75
all_pins[14]	transitions[0x1=>0x0]	376644	1			T38	24		T39	58		T70	7
all_pins[15]	values[0x0]	1033640	1			T43	1		T44	1		T45	1
all_pins[15]	values[0x1]	631983	1			T31	4		T38	51		T39	102
all_pins[15]	transitions[0x0=>0x1]	378551	1			T31	3		T38	42		T39	37
all_pins[15]	transitions[0x1=>0x0]	375514	1			T31	1		T38	53		T39	74
all_pins[16]	values[0x0]	1039032	1			T43	1		T44	1		T45	1
all_pins[16]	values[0x1]	626591	1			T31	16		T38	70		T39	102
all_pins[16]	transitions[0x0=>0x1]	374983	1			T31	14		T38	51		T39	27
all_pins[16]	transitions[0x1=>0x0]	380375	1			T31	2		T38	32		T39	27
all_pins[17]	values[0x0]	1034554	1			T43	1		T44	1		T45	1
all_pins[17]	values[0x1]	631069	1			T31	11		T38	56		T39	85
all_pins[17]	transitions[0x0=>0x1]	379322	1			T31	3		T38	31		T39	45
all_pins[17]	transitions[0x1=>0x0]	374844	1			T31	8		T38	45		T39	62
all_pins[18]	values[0x0]	1034134	1			T43	1		T44	1		T45	1
all_pins[18]	values[0x1]	631489	1			T31	7		T38	61		T39	61
all_pins[18]	transitions[0x0=>0x1]	378380	1			T31	5		T38	42		T39	51
all_pins[18]	transitions[0x1=>0x0]	377960	1			T31	9		T38	37		T39	75
all_pins[19]	values[0x0]	1030980	1			T43	1		T44	1		T45	1
all_pins[19]	values[0x1]	634643	1			T31	9		T38	29		T39	98
all_pins[19]	transitions[0x0=>0x1]	378702	1			T31	5		T38	14		T39	89
all_pins[19]	transitions[0x1=>0x0]	375548	1			T31	3		T38	46		T39	52
all_pins[20]	values[0x0]	1037136	1			T43	1		T44	1		T45	1
all_pins[20]	values[0x1]	628487	1			T31	5		T38	85		T39	148
all_pins[20]	transitions[0x0=>0x1]	373229	1			T31	1		T38	77		T39	84
all_pins[20]	transitions[0x1=>0x0]	379385	1			T31	5		T38	21		T39	34
all_pins[21]	values[0x0]	1034043	1			T43	1		T44	1		T45	1
all_pins[21]	values[0x1]	631580	1			T31	3		T38	74		T39	100
all_pins[21]	transitions[0x0=>0x1]	379224	1			T31	3		T38	36		T39	39
all_pins[21]	transitions[0x1=>0x0]	376131	1			T31	5		T38	47		T39	87
all_pins[22]	values[0x0]	1033298	1			T43	1		T44	1		T45	1
all_pins[22]	values[0x1]	632325	1			T31	10		T38	69		T39	128
all_pins[22]	transitions[0x0=>0x1]	376975	1			T31	10		T38	41		T39	78
all_pins[22]	transitions[0x1=>0x0]	376230	1			T31	3		T38	46		T39	50
all_pins[23]	values[0x0]	1034467	1			T43	1		T44	1		T45	1
all_pins[23]	values[0x1]	631156	1			T38	71		T39	100		T70	26
all_pins[23]	transitions[0x0=>0x1]	377073	1			T38	39		T39	56		T70	22
all_pins[23]	transitions[0x1=>0x0]	378242	1			T31	10		T38	37		T39	84
all_pins[24]	values[0x0]	1031749	1			T43	1		T44	1		T45	1
all_pins[24]	values[0x1]	633874	1			T31	13		T38	60		T39	79
all_pins[24]	transitions[0x0=>0x1]	378299	1			T31	13		T38	40		T39	30
all_pins[24]	transitions[0x1=>0x0]	375581	1			T38	51		T39	51		T70	11
all_pins[25]	values[0x0]	1038504	1			T43	1		T44	1		T45	1
all_pins[25]	values[0x1]	627119	1			T31	11		T38	58		T39	83
all_pins[25]	transitions[0x0=>0x1]	372450	1			T31	4		T38	37		T39	49
all_pins[25]	transitions[0x1=>0x0]	379205	1			T31	6		T38	39		T39	45
all_pins[26]	values[0x0]	1034079	1			T43	1		T44	1		T45	1
all_pins[26]	values[0x1]	631544	1			T31	1		T38	76		T39	56
all_pins[26]	transitions[0x0=>0x1]	378425	1			T38	44		T39	30		T70	10
all_pins[26]	transitions[0x1=>0x0]	374000	1			T31	10		T38	26		T39	57
all_pins[27]	values[0x0]	1038004	1			T43	1		T44	1		T45	1
all_pins[27]	values[0x1]	627619	1			T31	8		T38	63		T39	154
all_pins[27]	transitions[0x0=>0x1]	374684	1			T31	8		T38	30		T39	111
all_pins[27]	transitions[0x1=>0x0]	378609	1			T31	1		T38	43		T39	13
all_pins[28]	values[0x0]	1032769	1			T43	1		T44	1		T45	1
all_pins[28]	values[0x1]	632854	1			T31	14		T38	81		T39	99
all_pins[28]	transitions[0x0=>0x1]	380751	1			T31	9		T38	39		T39	38
all_pins[28]	transitions[0x1=>0x0]	375516	1			T31	3		T38	21		T39	93
all_pins[29]	values[0x0]	1030539	1			T43	1		T44	1		T45	1
all_pins[29]	values[0x1]	635084	1			T31	13		T38	45		T39	108
all_pins[29]	transitions[0x0=>0x1]	378184	1			T31	10		T38	18		T39	72
all_pins[29]	transitions[0x1=>0x0]	375954	1			T31	11		T38	54		T39	63
all_pins[30]	values[0x0]	1038128	1			T43	1		T44	1		T45	1
all_pins[30]	values[0x1]	627495	1			T31	5		T38	49		T39	62
all_pins[30]	transitions[0x0=>0x1]	373014	1			T31	1		T38	33		T39	25
all_pins[30]	transitions[0x1=>0x0]	380603	1			T31	9		T38	29		T39	71
all_pins[31]	values[0x0]	1036601	1			T43	1		T44	1		T45	1
all_pins[31]	values[0x1]	629022	1			T31	8		T38	54		T39	138
all_pins[31]	transitions[0x0=>0x1]	376130	1			T31	6		T38	34		T39	91
all_pins[31]	transitions[0x1=>0x0]	374603	1			T31	3		T38	29		T39	15