Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	6572925	1			T43	27		T44	143		T45	1
all_values[1]	6572925	1			T43	27		T44	143		T45	1
all_values[2]	6572925	1			T43	27		T44	143		T45	1
all_values[3]	6572925	1			T43	27		T44	143		T45	1
all_values[4]	6572925	1			T43	27		T44	143		T45	1
all_values[5]	6572925	1			T43	27		T44	143		T45	1
all_values[6]	6572925	1			T43	27		T44	143		T45	1
all_values[7]	6572925	1			T43	27		T44	143		T45	1
all_values[8]	6572925	1			T43	27		T44	143		T45	1
all_values[9]	6572925	1			T43	27		T44	143		T45	1
all_values[10]	6572925	1			T43	27		T44	143		T45	1
all_values[11]	6572925	1			T43	27		T44	143		T45	1
all_values[12]	6572925	1			T43	27		T44	143		T45	1
all_values[13]	6572925	1			T43	27		T44	143		T45	1
all_values[14]	6572925	1			T43	27		T44	143		T45	1
all_values[15]	6572925	1			T43	27		T44	143		T45	1
all_values[16]	6572925	1			T43	27		T44	143		T45	1
all_values[17]	6572925	1			T43	27		T44	143		T45	1
all_values[18]	6572925	1			T43	27		T44	143		T45	1
all_values[19]	6572925	1			T43	27		T44	143		T45	1
all_values[20]	6572925	1			T43	27		T44	143		T45	1
all_values[21]	6572925	1			T43	27		T44	143		T45	1
all_values[22]	6572925	1			T43	27		T44	143		T45	1
all_values[23]	6572925	1			T43	27		T44	143		T45	1
all_values[24]	6572925	1			T43	27		T44	143		T45	1
all_values[25]	6572925	1			T43	27		T44	143		T45	1
all_values[26]	6572925	1			T43	27		T44	143		T45	1
all_values[27]	6572925	1			T43	27		T44	143		T45	1
all_values[28]	6572925	1			T43	27		T44	143		T45	1
all_values[29]	6572925	1			T43	27		T44	143		T45	1
all_values[30]	6572925	1			T43	27		T44	143		T45	1
all_values[31]	6572925	1			T43	27		T44	143		T45	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138320556

1

T43

864

T44

4576

T45

32

auto[1]

72013044

1

T31

647

T38

4190

T39

9664

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80260893

1

T43

864

T44

4576

T45

32

auto[1]

130072707

1

T31

845

T38

6565

T39

17049

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

208378625

1

T43

864

T44

4576

T45

32

auto[1]

1954975

1

T31

110

T49

201

T48

118

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2280682	1			T43	27		T44	143		T45	1
all_values[0]	auto[0]	auto[0]	auto[1]	2027263	1			T31	3		T38	107		T39	332
all_values[0]	auto[0]	auto[1]	auto[0]	227073	1			T31	9		T38	22		T39	21
all_values[0]	auto[0]	auto[1]	auto[1]	1976914	1			T31	21		T38	120		T39	267
all_values[0]	auto[1]	auto[0]	auto[1]	30710	1			T31	2		T49	3		T120	13
all_values[0]	auto[1]	auto[1]	auto[1]	30283	1			T31	2		T49	3		T48	2
all_values[1]	auto[0]	auto[0]	auto[0]	2282294	1			T43	27		T44	143		T45	1
all_values[1]	auto[0]	auto[0]	auto[1]	2007729	1			T31	20		T38	117		T39	140
all_values[1]	auto[0]	auto[1]	auto[0]	226534	1			T31	6		T38	21		T39	52
all_values[1]	auto[0]	auto[1]	auto[1]	1995293	1			T31	9		T38	96		T39	369
all_values[1]	auto[1]	auto[0]	auto[1]	30769	1			T49	4		T48	2		T120	15
all_values[1]	auto[1]	auto[1]	auto[1]	30306	1			T31	2		T49	2		T48	1
all_values[2]	auto[0]	auto[0]	auto[0]	2280307	1			T43	27		T44	143		T45	1
all_values[2]	auto[0]	auto[0]	auto[1]	1997176	1			T31	20		T38	94		T39	332
all_values[2]	auto[0]	auto[1]	auto[0]	227482	1			T31	6		T38	32		T39	16
all_values[2]	auto[0]	auto[1]	auto[1]	2006702	1			T31	12		T38	113		T39	219
all_values[2]	auto[1]	auto[0]	auto[1]	30864	1			T31	3		T49	4		T48	3
all_values[2]	auto[1]	auto[1]	auto[1]	30394	1			T31	1		T49	2		T48	1
all_values[3]	auto[0]	auto[0]	auto[0]	2284507	1			T43	27		T44	143		T45	1
all_values[3]	auto[0]	auto[0]	auto[1]	2028206	1			T31	25		T38	74		T39	383
all_values[3]	auto[0]	auto[1]	auto[0]	229212	1			T31	5		T38	15		T39	19
all_values[3]	auto[0]	auto[1]	auto[1]	1969660	1			T31	2		T38	156		T39	142
all_values[3]	auto[1]	auto[0]	auto[1]	30722	1			T31	2		T49	4		T48	4
all_values[3]	auto[1]	auto[1]	auto[1]	30618	1			T49	5		T48	2		T120	9
all_values[4]	auto[0]	auto[0]	auto[0]	2283794	1			T43	27		T44	143		T45	1
all_values[4]	auto[0]	auto[0]	auto[1]	2025922	1			T31	19		T38	144		T39	131
all_values[4]	auto[0]	auto[1]	auto[0]	225303	1			T31	7		T38	30		T39	48
all_values[4]	auto[0]	auto[1]	auto[1]	1976933	1			T31	6		T38	74		T39	329
all_values[4]	auto[1]	auto[0]	auto[1]	30634	1			T31	3		T49	3		T48	3
all_values[4]	auto[1]	auto[1]	auto[1]	30339	1			T31	2		T49	5		T48	3
all_values[5]	auto[0]	auto[0]	auto[0]	2282398	1			T43	27		T44	143		T45	1
all_values[5]	auto[0]	auto[0]	auto[1]	2015893	1			T38	90		T39	175		T70	51
all_values[5]	auto[0]	auto[1]	auto[0]	228768	1			T31	8		T38	27		T39	31
all_values[5]	auto[0]	auto[1]	auto[1]	1984945	1			T31	15		T38	119		T39	389
all_values[5]	auto[1]	auto[0]	auto[1]	30807	1			T31	1		T49	7		T48	3
all_values[5]	auto[1]	auto[1]	auto[1]	30114	1			T31	2		T48	2		T120	2
all_values[6]	auto[0]	auto[0]	auto[0]	2276897	1			T43	27		T44	143		T45	1
all_values[6]	auto[0]	auto[0]	auto[1]	2000283	1			T31	21		T38	104		T39	355
all_values[6]	auto[0]	auto[1]	auto[0]	223131	1			T31	7		T38	25		T39	17
all_values[6]	auto[0]	auto[1]	auto[1]	2011590	1			T31	9		T38	113		T39	194
all_values[6]	auto[1]	auto[0]	auto[1]	30850	1			T31	2		T49	2		T48	3
all_values[6]	auto[1]	auto[1]	auto[1]	30174	1			T31	3		T49	4		T120	18
all_values[7]	auto[0]	auto[0]	auto[0]	2282201	1			T43	27		T44	143		T45	1
all_values[7]	auto[0]	auto[0]	auto[1]	2020602	1			T31	14		T38	82		T39	292
all_values[7]	auto[0]	auto[1]	auto[0]	225278	1			T31	7		T38	12		T39	19
all_values[7]	auto[0]	auto[1]	auto[1]	1983858	1			T31	16		T38	130		T39	280
all_values[7]	auto[1]	auto[0]	auto[1]	30705	1			T31	1		T49	4		T48	7
all_values[7]	auto[1]	auto[1]	auto[1]	30281	1			T31	3		T49	4		T120	15
all_values[8]	auto[0]	auto[0]	auto[0]	2279371	1			T43	27		T44	143		T45	1
all_values[8]	auto[0]	auto[0]	auto[1]	2005651	1			T31	9		T38	130		T39	370
all_values[8]	auto[0]	auto[1]	auto[0]	229957	1			T31	6		T38	16		T39	15
all_values[8]	auto[0]	auto[1]	auto[1]	1996917	1			T31	15		T38	87		T39	190
all_values[8]	auto[1]	auto[0]	auto[1]	30757	1			T31	3		T49	5		T48	2
all_values[8]	auto[1]	auto[1]	auto[1]	30272	1			T31	2		T49	1		T48	2
all_values[9]	auto[0]	auto[0]	auto[0]	2282385	1			T43	27		T44	143		T45	1
all_values[9]	auto[0]	auto[0]	auto[1]	1993948	1			T31	21		T38	108		T39	485
all_values[9]	auto[0]	auto[1]	auto[0]	230939	1			T31	4		T38	20		T39	13
all_values[9]	auto[0]	auto[1]	auto[1]	2004559	1			T31	5		T38	106		T39	88
all_values[9]	auto[1]	auto[0]	auto[1]	30597	1			T31	4		T49	1		T48	1
all_values[9]	auto[1]	auto[1]	auto[1]	30497	1			T31	2		T49	3		T48	3
all_values[10]	auto[0]	auto[0]	auto[0]	2280776	1			T43	27		T44	143		T45	1
all_values[10]	auto[0]	auto[0]	auto[1]	2020637	1			T31	13		T38	150		T39	356
all_values[10]	auto[0]	auto[1]	auto[0]	222442	1			T31	14		T38	13		T39	15
all_values[10]	auto[0]	auto[1]	auto[1]	1988249	1			T31	15		T38	76		T39	232
all_values[10]	auto[1]	auto[0]	auto[1]	30520	1			T31	1		T49	3		T48	2
all_values[10]	auto[1]	auto[1]	auto[1]	30301	1			T31	1		T49	2		T48	1
all_values[11]	auto[0]	auto[0]	auto[0]	2283497	1			T43	27		T44	143		T45	1
all_values[11]	auto[0]	auto[0]	auto[1]	2006178	1			T31	3		T38	84		T39	143
all_values[11]	auto[0]	auto[1]	auto[0]	228509	1			T31	16		T38	21		T39	77
all_values[11]	auto[0]	auto[1]	auto[1]	1993542	1			T31	11		T38	121		T39	244
all_values[11]	auto[1]	auto[0]	auto[1]	30886	1			T31	2		T49	5		T48	1
all_values[11]	auto[1]	auto[1]	auto[1]	30313	1			T31	1		T49	2		T48	2
all_values[12]	auto[0]	auto[0]	auto[0]	2280650	1			T43	27		T44	143		T45	1
all_values[12]	auto[0]	auto[0]	auto[1]	2005675	1			T31	5		T38	106		T39	273
all_values[12]	auto[0]	auto[1]	auto[0]	227475	1			T31	11		T38	19		T39	26
all_values[12]	auto[0]	auto[1]	auto[1]	1998030	1			T31	16		T38	90		T39	250
all_values[12]	auto[1]	auto[0]	auto[1]	30636	1			T31	2		T49	4		T48	4
all_values[12]	auto[1]	auto[1]	auto[1]	30459	1			T31	3		T49	1		T48	1
all_values[13]	auto[0]	auto[0]	auto[0]	2280288	1			T43	27		T44	143		T45	1
all_values[13]	auto[0]	auto[0]	auto[1]	2009439	1			T31	26		T38	112		T39	213
all_values[13]	auto[0]	auto[1]	auto[0]	228920	1			T31	6		T38	42		T39	77
all_values[13]	auto[0]	auto[1]	auto[1]	1993273	1			T38	72		T39	315		T70	31
all_values[13]	auto[1]	auto[0]	auto[1]	31051	1			T49	1		T48	1		T120	9
all_values[13]	auto[1]	auto[1]	auto[1]	29954	1			T49	7		T48	2		T120	12
all_values[14]	auto[0]	auto[0]	auto[0]	2280080	1			T43	27		T44	143		T45	1
all_values[14]	auto[0]	auto[0]	auto[1]	2007771	1			T31	20		T38	68		T39	193
all_values[14]	auto[0]	auto[1]	auto[0]	227836	1			T31	3		T38	79		T39	18
all_values[14]	auto[0]	auto[1]	auto[1]	1996182	1			T31	1		T38	98		T39	344
all_values[14]	auto[1]	auto[0]	auto[1]	30701	1			T31	3		T49	2		T48	5
all_values[14]	auto[1]	auto[1]	auto[1]	30355	1			T31	1		T48	1		T120	12
all_values[15]	auto[0]	auto[0]	auto[0]	2280255	1			T43	27		T44	143		T45	1
all_values[15]	auto[0]	auto[0]	auto[1]	2005740	1			T31	4		T38	115		T39	179
all_values[15]	auto[0]	auto[1]	auto[0]	221980	1			T31	9		T38	30		T39	35
all_values[15]	auto[0]	auto[1]	auto[1]	2003845	1			T31	2		T38	90		T39	284
all_values[15]	auto[1]	auto[0]	auto[1]	30421	1			T31	2		T49	3		T48	1
all_values[15]	auto[1]	auto[1]	auto[1]	30684	1			T31	1		T120	14		T121	28
all_values[16]	auto[0]	auto[0]	auto[0]	2282282	1			T43	27		T44	143		T45	1
all_values[16]	auto[0]	auto[0]	auto[1]	2027467	1			T31	5		T38	96		T39	213
all_values[16]	auto[0]	auto[1]	auto[0]	229966	1			T31	12		T38	28		T39	87
all_values[16]	auto[0]	auto[1]	auto[1]	1972034	1			T31	20		T38	120		T39	293
all_values[16]	auto[1]	auto[0]	auto[1]	30699	1			T49	1		T48	3		T120	15
all_values[16]	auto[1]	auto[1]	auto[1]	30477	1			T31	4		T49	5		T48	1
all_values[17]	auto[0]	auto[0]	auto[0]	2281397	1			T43	27		T44	143		T45	1
all_values[17]	auto[0]	auto[0]	auto[1]	2014786	1			T31	11		T38	113		T39	279
all_values[17]	auto[0]	auto[1]	auto[0]	223934	1			T31	9		T38	13		T39	99
all_values[17]	auto[0]	auto[1]	auto[1]	1992050	1			T31	14		T38	92		T39	216
all_values[17]	auto[1]	auto[0]	auto[1]	30381	1			T31	3		T49	3		T48	4
all_values[17]	auto[1]	auto[1]	auto[1]	30377	1			T31	2		T49	4		T48	1
all_values[18]	auto[0]	auto[0]	auto[0]	2280858	1			T43	27		T44	143		T45	1
all_values[18]	auto[0]	auto[0]	auto[1]	1990777	1			T31	20		T38	117		T39	387
all_values[18]	auto[0]	auto[1]	auto[0]	229516	1			T31	7		T38	17		T39	22
all_values[18]	auto[0]	auto[1]	auto[1]	2010669	1			T31	10		T38	101		T39	162
all_values[18]	auto[1]	auto[0]	auto[1]	31016	1			T31	4		T49	3		T48	1
all_values[18]	auto[1]	auto[1]	auto[1]	30089	1			T49	6		T48	1		T120	13
all_values[19]	auto[0]	auto[0]	auto[0]	2277512	1			T43	27		T44	143		T45	1
all_values[19]	auto[0]	auto[0]	auto[1]	2008011	1			T31	3		T38	145		T39	235
all_values[19]	auto[0]	auto[1]	auto[0]	227800	1			T31	17		T38	13		T39	79
all_values[19]	auto[0]	auto[1]	auto[1]	1998576	1			T31	11		T38	56		T39	262
all_values[19]	auto[1]	auto[0]	auto[1]	30655	1			T31	1		T49	1		T48	1
all_values[19]	auto[1]	auto[1]	auto[1]	30371	1			T31	1		T49	3		T48	2
all_values[20]	auto[0]	auto[0]	auto[0]	2281982	1			T43	27		T44	143		T45	1
all_values[20]	auto[0]	auto[0]	auto[1]	2015225	1			T31	13		T38	69		T39	214
all_values[20]	auto[0]	auto[1]	auto[0]	226772	1			T31	21		T38	41		T39	12
all_values[20]	auto[0]	auto[1]	auto[1]	1988105	1			T31	5		T38	138		T39	381
all_values[20]	auto[1]	auto[0]	auto[1]	30586	1			T31	1		T49	7		T48	3
all_values[20]	auto[1]	auto[1]	auto[1]	30255	1			T49	2		T48	2		T120	16
all_values[21]	auto[0]	auto[0]	auto[0]	2283032	1			T43	27		T44	143		T45	1
all_values[21]	auto[0]	auto[0]	auto[1]	2003051	1			T31	11		T38	83		T39	245
all_values[21]	auto[0]	auto[1]	auto[0]	224167	1			T31	16		T38	22		T39	65
all_values[21]	auto[0]	auto[1]	auto[1]	2001545	1			T31	2		T38	116		T39	295
all_values[21]	auto[1]	auto[0]	auto[1]	30890	1			T31	3		T49	4		T48	4
all_values[21]	auto[1]	auto[1]	auto[1]	30240	1			T49	6		T48	1		T120	14
all_values[22]	auto[0]	auto[0]	auto[0]	2280259	1			T43	27		T44	143		T45	1
all_values[22]	auto[0]	auto[0]	auto[1]	2004941	1			T31	20		T38	95		T39	234
all_values[22]	auto[0]	auto[1]	auto[0]	227498	1			T31	8		T38	10		T39	16
all_values[22]	auto[0]	auto[1]	auto[1]	1998905	1			T31	12		T38	120		T39	316
all_values[22]	auto[1]	auto[0]	auto[1]	31021	1			T31	1		T49	4		T48	2
all_values[22]	auto[1]	auto[1]	auto[1]	30301	1			T31	1		T49	2		T48	1
all_values[23]	auto[0]	auto[0]	auto[0]	2280655	1			T43	27		T44	143		T45	1
all_values[23]	auto[0]	auto[0]	auto[1]	2000863	1			T31	18		T38	97		T39	250
all_values[23]	auto[0]	auto[1]	auto[0]	230225	1			T31	4		T38	34		T39	66
all_values[23]	auto[0]	auto[1]	auto[1]	1999798	1			T38	113		T39	260		T70	53
all_values[23]	auto[1]	auto[0]	auto[1]	30654	1			T31	2		T49	2		T48	1
all_values[23]	auto[1]	auto[1]	auto[1]	30730	1			T49	3		T120	18		T121	34
all_values[24]	auto[0]	auto[0]	auto[0]	2279182	1			T43	27		T44	143		T45	1
all_values[24]	auto[0]	auto[0]	auto[1]	1995650	1			T31	7		T38	103		T39	387
all_values[24]	auto[0]	auto[1]	auto[0]	223690	1			T31	6		T38	42		T39	14
all_values[24]	auto[0]	auto[1]	auto[1]	2013065	1			T31	19		T38	98		T39	195
all_values[24]	auto[1]	auto[0]	auto[1]	31033	1			T31	4		T49	2		T48	3
all_values[24]	auto[1]	auto[1]	auto[1]	30305	1			T49	3		T48	1		T120	13
all_values[25]	auto[0]	auto[0]	auto[0]	2281267	1			T43	27		T44	143		T45	1
all_values[25]	auto[0]	auto[0]	auto[1]	2025280	1			T31	12		T38	81		T39	268
all_values[25]	auto[0]	auto[1]	auto[0]	225003	1			T31	12		T38	30		T39	41
all_values[25]	auto[0]	auto[1]	auto[1]	1980194	1			T31	16		T38	99		T39	241
all_values[25]	auto[1]	auto[0]	auto[1]	31071	1			T31	2		T49	6		T48	1
all_values[25]	auto[1]	auto[1]	auto[1]	30110	1			T31	1		T49	2		T48	2
all_values[26]	auto[0]	auto[0]	auto[0]	2279272	1			T43	27		T44	143		T45	1
all_values[26]	auto[0]	auto[0]	auto[1]	2014159	1			T31	14		T38	85		T39	359
all_values[26]	auto[0]	auto[1]	auto[0]	223640	1			T31	6		T38	25		T39	82
all_values[26]	auto[0]	auto[1]	auto[1]	1994547	1			T31	1		T38	126		T39	140
all_values[26]	auto[1]	auto[0]	auto[1]	30847	1			T31	3		T49	5		T48	2
all_values[26]	auto[1]	auto[1]	auto[1]	30460	1			T49	2		T48	1		T120	10
all_values[27]	auto[0]	auto[0]	auto[0]	2287528	1			T43	27		T44	143		T45	1
all_values[27]	auto[0]	auto[0]	auto[1]	2017170	1			T31	11		T38	92		T39	220
all_values[27]	auto[0]	auto[1]	auto[0]	225875	1			T31	3		T38	31		T39	18
all_values[27]	auto[0]	auto[1]	auto[1]	1981309	1			T31	10		T38	105		T39	381
all_values[27]	auto[1]	auto[0]	auto[1]	30748	1			T31	3		T49	3		T48	2
all_values[27]	auto[1]	auto[1]	auto[1]	30295	1			T31	2		T49	3		T48	1
all_values[28]	auto[0]	auto[0]	auto[0]	2280883	1			T43	27		T44	143		T45	1
all_values[28]	auto[0]	auto[0]	auto[1]	2016436	1			T31	5		T38	77		T39	301
all_values[28]	auto[0]	auto[1]	auto[0]	223623	1			T31	7		T38	23		T39	33
all_values[28]	auto[0]	auto[1]	auto[1]	1991009	1			T31	20		T38	129		T39	257
all_values[28]	auto[1]	auto[0]	auto[1]	30797	1			T31	3		T49	5		T48	2
all_values[28]	auto[1]	auto[1]	auto[1]	30177	1			T31	2		T49	2		T48	1
all_values[29]	auto[0]	auto[0]	auto[0]	2281193	1			T43	27		T44	143		T45	1
all_values[29]	auto[0]	auto[0]	auto[1]	1995342	1			T31	12		T38	107		T39	221
all_values[29]	auto[0]	auto[1]	auto[0]	230245	1			T31	10		T38	23		T39	56
all_values[29]	auto[0]	auto[1]	auto[1]	2005100	1			T31	11		T38	84		T39	268
all_values[29]	auto[1]	auto[0]	auto[1]	30570	1			T31	3		T49	2		T48	3
all_values[29]	auto[1]	auto[1]	auto[1]	30475	1			T31	2		T49	2		T120	11
all_values[30]	auto[0]	auto[0]	auto[0]	2283832	1			T43	27		T44	143		T45	1
all_values[30]	auto[0]	auto[0]	auto[1]	2007373	1			T31	17		T38	91		T39	335
all_values[30]	auto[0]	auto[1]	auto[0]	225651	1			T31	8		T38	56		T39	58
all_values[30]	auto[0]	auto[1]	auto[1]	1994935	1			T31	3		T38	74		T39	177
all_values[30]	auto[1]	auto[0]	auto[1]	30683	1			T31	2		T49	4		T48	2
all_values[30]	auto[1]	auto[1]	auto[1]	30451	1			T31	1		T49	2		T48	2
all_values[31]	auto[0]	auto[0]	auto[0]	2289086	1			T43	27		T44	143		T45	1
all_values[31]	auto[0]	auto[0]	auto[1]	2011065	1			T31	10		T38	107		T39	168
all_values[31]	auto[0]	auto[1]	auto[0]	221847	1			T31	12		T38	36		T39	36
all_values[31]	auto[0]	auto[1]	auto[1]	1989690	1			T31	14		T38	90		T39	401
all_values[31]	auto[1]	auto[0]	auto[1]	30964	1			T31	2		T49	4		T48	2
all_values[31]	auto[1]	auto[1]	auto[1]	30273	1			T49	2		T120	11		T121	28

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal