Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[1]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[2]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[3]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[4]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[5]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[6]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[7]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[8]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[9]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[10]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[11]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[12]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[13]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[14]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[15]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[16]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[17]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[18]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[19]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[20]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[21]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[22]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[23]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[24]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[25]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[26]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[27]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[28]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[29]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[30]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[31]	6497550	1			T43	50		T44	285		T45	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110680158

1

T43

1321

T44

7412

T45

32

auto[1]

97241442

1

T43

279

T44

1708

T46

736

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172531656

1

T43

1376

T44

6961

T45

32

auto[1]

35389944

1

T43

224

T44

2159

T46

609

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162235477

1

T43

926

T44

4634

T45

32

auto[1]

45686123

1

T43

674

T44

4486

T46

1785

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	2352604	1			T43	10		T44	71		T45	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2160430	1			T43	2		T44	7		T46	4
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	556781	1			T44	39		T46	13		T47	6
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	541846	1			T43	30		T44	121		T46	33
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	335289	1			T44	6		T46	17		T47	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	550600	1			T43	8		T44	41		T46	15
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	2355939	1			T43	24		T44	127		T45	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2158371	1			T44	13		T46	5		T47	13
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	556017	1			T43	4		T44	31		T46	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	538748	1			T43	20		T44	93		T46	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	336264	1			T43	2		T44	7		T46	9
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	552211	1			T44	14		T46	15		T47	4
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	2357274	1			T43	7		T44	121		T45	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2155845	1			T43	1		T44	10		T46	4
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	556331	1			T44	18		T46	6		T47	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	541680	1			T43	22		T44	89		T46	23
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	334359	1			T43	1		T44	17		T46	8
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	552061	1			T43	19		T44	30		T46	4
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	2364400	1			T43	22		T44	98		T45	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2145836	1			T43	5		T44	8		T47	17
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	556292	1			T43	3		T44	32		T46	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	543418	1			T43	7		T44	102		T46	74
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	334632	1			T43	1		T44	8		T46	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	552972	1			T43	12		T44	37		T46	13
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	2361847	1			T43	10		T44	116		T45	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2154341	1			T43	2		T44	8		T46	2
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	558114	1			T43	8		T44	28		T46	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	537666	1			T43	26		T44	85		T46	51
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	334659	1			T43	2		T44	8		T46	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	550923	1			T43	2		T44	40		T46	8
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	2359782	1			T43	7		T44	90		T45	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2155945	1			T43	5		T44	14		T46	11
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	558610	1			T43	4		T44	39		T46	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	538930	1			T43	16		T44	94		T46	33
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	333530	1			T43	1		T44	8		T46	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	550753	1			T43	17		T44	40		T46	10
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	2362329	1			T43	10		T44	66		T45	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2151701	1			T43	6		T44	2		T46	4
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	559221	1			T43	13		T44	32		T46	21
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	539413	1			T43	12		T44	123		T46	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	334610	1			T43	1		T44	14		T46	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	550276	1			T43	8		T44	48		T46	16
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	2357341	1			T43	37		T44	91		T45	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2153258	1			T43	3		T44	8		T46	7
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	554640	1			T43	3		T44	30		T46	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	543146	1			T43	2		T44	90		T46	35
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	339107	1			T44	9		T46	5		T47	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	550058	1			T43	5		T44	57		T47	10
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	2359441	1			T43	7		T44	124		T45	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2149874	1			T43	1		T44	16		T46	15
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	556569	1			T43	3		T44	58		T46	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	541079	1			T43	32		T44	58		T46	29
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	338576	1			T43	2		T44	5		T47	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	552011	1			T43	5		T44	24		T47	8
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	2371031	1			T43	38		T44	67		T45	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2143882	1			T43	4		T44	6		T46	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	558346	1			T43	6		T44	38		T46	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	541179	1			T43	2		T44	119		T46	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	331621	1			T44	12		T46	13		T47	27
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	551491	1			T44	43		T46	6		T47	10
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	2366482	1			T43	6		T44	119		T45	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2149837	1			T43	4		T44	14		T46	6
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	561037	1			T43	5		T44	27		T47	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	536183	1			T43	24		T44	74		T46	53
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	332531	1			T43	4		T44	9		T46	6
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	551480	1			T43	7		T44	42		T46	7
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	2362195	1			T43	20		T44	81		T45	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2151418	1			T43	4		T44	7		T46	3
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	554720	1			T43	9		T44	39		T46	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	543072	1			T43	11		T44	97		T46	57
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	334878	1			T43	1		T44	13		T46	15
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	551267	1			T43	5		T44	48		T46	16
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	2361534	1			T43	36		T44	123		T45	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2150496	1			T43	2		T44	6		T46	3
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	557203	1			T43	2		T44	25		T46	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	540037	1			T43	7		T44	100		T46	46
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	334970	1			T43	1		T44	12		T46	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	553310	1			T43	2		T44	19		T46	19
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	2364489	1			T43	7		T44	87		T45	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2151287	1			T43	5		T44	12		T46	4
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	556567	1			T43	3		T44	33		T46	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	541417	1			T43	16		T44	106		T46	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	333341	1			T43	1		T44	8		T46	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	550449	1			T43	18		T44	39		T46	15
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	2357851	1			T43	36		T44	118		T45	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2152827	1			T43	4		T44	9		T46	3
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	554694	1			T43	10		T44	30		T46	22
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	545163	1			T44	81		T46	42		T47	64
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	336194	1			T44	12		T46	12		T47	10
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	550821	1			T44	35		T46	2		T47	18
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	2355298	1			T43	8		T44	87		T45	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2157050	1			T43	4		T44	11		T46	7
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	558208	1			T44	25		T46	13		T47	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	540551	1			T43	26		T44	97		T46	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	333674	1			T43	2		T44	12		T46	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	552769	1			T43	10		T44	53		T46	16
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	2374002	1			T43	38		T44	129		T45	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2145836	1			T43	4		T44	12		T47	9
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	555590	1			T43	3		T44	49		T46	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	540068	1			T43	5		T44	78		T46	59
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	335596	1			T44	4		T46	16		T47	26
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	546458	1			T44	13		T46	16		T47	12
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	2358583	1			T43	34		T44	133		T45	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2159581	1			T43	6		T44	17		T46	9
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	556452	1			T44	21		T46	20		T47	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	540390	1			T43	10		T44	87		T46	11
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	332183	1			T44	7		T47	23		T31	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	550361	1			T44	20		T46	3		T47	14
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	2364988	1			T43	42		T44	102		T45	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2146384	1			T43	6		T44	13		T46	12
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	555075	1			T43	2		T44	28		T46	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	544306	1			T44	102		T46	26		T47	80
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	337032	1			T44	7		T46	4		T47	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	549765	1			T44	33		T46	9		T47	18
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	2362907	1			T43	38		T44	113		T45	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2148501	1			T43	2		T44	7		T46	15
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	551643	1			T44	15		T47	12		T31	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	544405	1			T43	10		T44	113		T46	35
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	338461	1			T44	8		T46	3		T47	12
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	551633	1			T44	29		T46	5		T47	10
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	2360812	1			T43	41		T44	129		T45	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2153753	1			T43	7		T44	8		T46	7
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	554230	1			T43	2		T44	27		T47	8
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	543675	1			T44	91		T46	34		T47	125
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	335293	1			T44	10		T46	9		T47	29
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	549787	1			T44	20		T46	15		T47	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	2362440	1			T43	18		T44	73		T45	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2153841	1			T43	2		T44	8		T46	6
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	551360	1			T44	51		T46	12		T47	6
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	542632	1			T43	26		T44	94		T46	45
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	335872	1			T43	2		T44	15		T46	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	551405	1			T43	2		T44	44		T46	11
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	2356929	1			T43	23		T44	86		T45	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2154311	1			T43	5		T44	8		T46	5
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	554408	1			T44	33		T46	2		T47	10
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	546784	1			T43	20		T44	117		T46	39
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	335814	1			T43	2		T44	14		T46	7
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	549304	1			T44	27		T46	2		T47	8
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	2360638	1			T43	15		T44	116		T45	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2156179	1			T43	3		T44	9		T46	3
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	551004	1			T44	51		T46	19		T47	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	540610	1			T43	30		T44	81		T46	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	338414	1			T43	2		T44	13		T46	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	550705	1			T44	15		T46	9		T47	4
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	2363087	1			T43	16		T44	108		T45	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2150217	1			T43	5		T44	12		T46	8
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	554711	1			T44	46		T46	12		T47	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	543565	1			T43	28		T44	82		T46	22
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	335758	1			T43	1		T44	5		T46	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	550212	1			T44	32		T46	2		T47	10
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	2362948	1			T43	28		T44	128		T45	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2152469	1			T44	12		T46	3		T47	12
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	553936	1			T44	20		T46	4		T31	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	540052	1			T43	19		T44	78		T46	49
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	338357	1			T43	3		T44	14		T46	16
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	549788	1			T44	33		T46	13		T47	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	2356626	1			T43	28		T44	89		T45	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2155652	1			T43	4		T44	4		T46	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	552155	1			T43	3		T44	47		T46	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	547676	1			T43	14		T44	106		T46	46
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	336934	1			T43	1		T44	11		T46	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	548507	1			T44	28		T46	13		T47	8
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	2358412	1			T43	39		T44	113		T45	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2160253	1			T43	1		T44	12		T46	5
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	555544	1			T44	65		T46	7		T47	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	540496	1			T43	2		T44	55		T46	46
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	336830	1			T44	9		T46	4		T47	27
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	546015	1			T43	8		T44	31		T46	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	2372450	1			T43	30		T44	101		T45	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2143838	1			T43	5		T44	10		T46	3
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	553301	1			T44	25		T46	9		T47	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	542937	1			T43	15		T44	107		T46	35
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	335818	1			T44	5		T46	8		T47	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	549206	1			T44	37		T46	4		T47	8
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	2360097	1			T43	7		T44	89		T45	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2157961	1			T43	1		T44	5		T46	7
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	554264	1			T44	28		T46	20		T47	16
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	543801	1			T43	37		T44	93		T46	19
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	334282	1			T43	2		T44	16		T46	4
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	547145	1			T43	3		T44	54		T46	10
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	2357417	1			T43	16		T44	86		T45	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2159687	1			T43	2		T44	5		T46	7
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	556911	1			T44	38		T46	10		T47	16
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	540107	1			T43	24		T44	124		T46	38
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	335209	1			T43	2		T44	12		T46	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	548219	1			T43	6		T44	20		T46	18
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	2360548	1			T43	33		T44	75		T45	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2152799	1			T43	3		T44	11		T46	5
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	555162	1			T43	4		T44	6		T46	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	543309	1			T43	10		T44	145		T46	45
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	336846	1			T44	9		T46	9		T47	24
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	548886	1			T44	39		T46	11		T47	12

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal