Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/gpio-sim-vcs/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[1]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[2]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[3]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[4]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[5]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[6]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[7]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[8]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[9]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[10]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[11]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[12]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[13]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[14]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[15]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[16]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[17]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[18]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[19]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[20]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[21]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[22]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[23]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[24]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[25]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[26]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[27]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[28]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[29]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[30]	6497550	1			T43	50		T44	285		T45	1
bins_for_gpio_bits[31]	6497550	1			T43	50		T44	285		T45	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110680158

1

T43

1321

T44

7412

T45

32

auto[1]

97241442

1

T43

279

T44

1708

T46

736

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110672392

1

T43

1310

T44

7403

T45

32

auto[1]

97249208

1

T43

290

T44

1717

T46

738

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	3351242	1			T43	39		T44	225		T45	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	99748	1			T44	6		T46	3		T47	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	99989	1			T43	1		T44	6		T46	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	2946571	1			T43	10		T44	48		T46	33
bins_for_gpio_bits[1]	auto[0]	auto[0]	3350851	1			T43	48		T44	248		T45	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	99616	1			T44	3		T46	3		T47	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	99853	1			T44	3		T46	3		T47	2
bins_for_gpio_bits[1]	auto[1]	auto[1]	2947230	1			T43	2		T44	31		T46	26
bins_for_gpio_bits[2]	auto[0]	auto[0]	3355293	1			T43	27		T44	221		T45	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	99720	1			T43	1		T44	7		T46	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	99992	1			T43	2		T44	7		T46	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	2942545	1			T43	20		T44	50		T46	15
bins_for_gpio_bits[3]	auto[0]	auto[0]	3364172	1			T43	30		T44	223		T45	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	99701	1			T43	1		T44	8		T46	5
bins_for_gpio_bits[3]	auto[1]	auto[0]	99938	1			T43	2		T44	9		T46	5
bins_for_gpio_bits[3]	auto[1]	auto[1]	2933739	1			T43	17		T44	45		T46	22
bins_for_gpio_bits[4]	auto[0]	auto[0]	3358081	1			T43	43		T44	222		T45	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	99262	1			T43	1		T44	7		T46	2
bins_for_gpio_bits[4]	auto[1]	auto[0]	99546	1			T43	1		T44	7		T46	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	2940661	1			T43	5		T44	49		T46	16
bins_for_gpio_bits[5]	auto[0]	auto[0]	3357804	1			T43	24		T44	215		T45	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	99259	1			T43	2		T44	7		T46	2
bins_for_gpio_bits[5]	auto[1]	auto[0]	99518	1			T43	3		T44	8		T46	2
bins_for_gpio_bits[5]	auto[1]	auto[1]	2940969	1			T43	21		T44	55		T46	27
bins_for_gpio_bits[6]	auto[0]	auto[0]	3361032	1			T43	32		T44	211		T45	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	99722	1			T43	2		T44	10		T46	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	99931	1			T43	3		T44	10		T46	4
bins_for_gpio_bits[6]	auto[1]	auto[1]	2936865	1			T43	13		T44	54		T46	24
bins_for_gpio_bits[7]	auto[0]	auto[0]	3355363	1			T43	41		T44	203		T45	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	99514	1			T43	1		T44	8		T47	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	99764	1			T43	1		T44	8		T47	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	2942909	1			T43	7		T44	66		T46	12
bins_for_gpio_bits[8]	auto[0]	auto[0]	3357605	1			T43	41		T44	234		T45	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	99220	1			T43	1		T44	5		T47	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	99484	1			T43	1		T44	6		T47	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	2941241	1			T43	7		T44	40		T46	15
bins_for_gpio_bits[9]	auto[0]	auto[0]	3370509	1			T43	46		T44	215		T45	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	99816	1			T44	9		T46	2		T47	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	100047	1			T44	9		T46	2		T47	4
bins_for_gpio_bits[9]	auto[1]	auto[1]	2927178	1			T43	4		T44	52		T46	18
bins_for_gpio_bits[10]	auto[0]	auto[0]	3363594	1			T43	32		T44	212		T45	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	99822	1			T43	2		T44	7		T46	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	100108	1			T43	3		T44	8		T46	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	2934026	1			T43	13		T44	58		T46	17
bins_for_gpio_bits[11]	auto[0]	auto[0]	3359838	1			T43	38		T44	209		T45	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	99906	1			T43	1		T44	8		T46	3
bins_for_gpio_bits[11]	auto[1]	auto[0]	100149	1			T43	2		T44	8		T46	3
bins_for_gpio_bits[11]	auto[1]	auto[1]	2937657	1			T43	9		T44	60		T46	31
bins_for_gpio_bits[12]	auto[0]	auto[0]	3358696	1			T43	44		T44	243		T45	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	99824	1			T43	1		T44	5		T46	5
bins_for_gpio_bits[12]	auto[1]	auto[0]	100078	1			T43	1		T44	5		T46	5
bins_for_gpio_bits[12]	auto[1]	auto[1]	2938952	1			T43	4		T44	32		T46	25
bins_for_gpio_bits[13]	auto[0]	auto[0]	3362830	1			T43	23		T44	217		T45	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	99436	1			T43	3		T44	9		T46	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	99643	1			T43	3		T44	9		T46	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	2935641	1			T43	21		T44	50		T46	25
bins_for_gpio_bits[14]	auto[0]	auto[0]	3358174	1			T43	46		T44	221		T45	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	99299	1			T44	8		T46	1		T47	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	99534	1			T44	8		T46	1		T47	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	2940543	1			T43	4		T44	48		T46	16
bins_for_gpio_bits[15]	auto[0]	auto[0]	3354081	1			T43	32		T44	198		T45	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	99775	1			T43	1		T44	11		T46	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	99976	1			T43	2		T44	11		T46	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	2943718	1			T43	15		T44	65		T46	25
bins_for_gpio_bits[16]	auto[0]	auto[0]	3370104	1			T43	46		T44	253		T45	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	99341	1			T44	3		T46	5		T47	4
bins_for_gpio_bits[16]	auto[1]	auto[0]	99556	1			T44	3		T46	5		T47	4
bins_for_gpio_bits[16]	auto[1]	auto[1]	2928549	1			T43	4		T44	26		T46	27
bins_for_gpio_bits[17]	auto[0]	auto[0]	3355868	1			T43	44		T44	235		T45	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	99320	1			T44	5		T46	1		T47	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	99557	1			T44	6		T46	2		T47	6
bins_for_gpio_bits[17]	auto[1]	auto[1]	2942805	1			T43	6		T44	39		T46	11
bins_for_gpio_bits[18]	auto[0]	auto[0]	3364567	1			T43	44		T44	224		T45	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	99526	1			T44	8		T46	3		T47	5
bins_for_gpio_bits[18]	auto[1]	auto[0]	99802	1			T44	8		T46	3		T47	5
bins_for_gpio_bits[18]	auto[1]	auto[1]	2933655	1			T43	6		T44	45		T46	22
bins_for_gpio_bits[19]	auto[0]	auto[0]	3358725	1			T43	48		T44	234		T45	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	99998	1			T44	7		T46	1		T47	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	100230	1			T44	7		T46	1		T47	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	2938597	1			T43	2		T44	37		T46	22
bins_for_gpio_bits[20]	auto[0]	auto[0]	3358860	1			T43	43		T44	243		T45	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	99625	1			T44	4		T46	4		T47	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	99857	1			T44	4		T46	4		T47	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	2939208	1			T43	7		T44	34		T46	27
bins_for_gpio_bits[21]	auto[0]	auto[0]	3356610	1			T43	43		T44	212		T45	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	99591	1			T43	1		T44	5		T46	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	99822	1			T43	1		T44	6		T46	4
bins_for_gpio_bits[21]	auto[1]	auto[1]	2941527	1			T43	5		T44	62		T46	16
bins_for_gpio_bits[22]	auto[0]	auto[0]	3358198	1			T43	43		T44	227		T45	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	99645	1			T44	8		T46	1		T47	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	99923	1			T44	9		T46	1		T47	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	2939784	1			T43	7		T44	41		T46	13
bins_for_gpio_bits[23]	auto[0]	auto[0]	3352424	1			T43	45		T44	245		T45	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	99583	1			T44	3		T46	2		T47	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	99828	1			T44	3		T46	3		T47	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	2945715	1			T43	5		T44	34		T46	20
bins_for_gpio_bits[24]	auto[0]	auto[0]	3361302	1			T43	44		T44	230		T45	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	99819	1			T44	6		T46	1		T47	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	100061	1			T44	6		T46	1		T47	4
bins_for_gpio_bits[24]	auto[1]	auto[1]	2936368	1			T43	6		T44	43		T46	14
bins_for_gpio_bits[25]	auto[0]	auto[0]	3357264	1			T43	47		T44	219		T45	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	99428	1			T44	6		T46	3		T47	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	99672	1			T44	7		T46	3		T47	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	2941186	1			T43	3		T44	53		T46	29
bins_for_gpio_bits[26]	auto[0]	auto[0]	3356671	1			T43	45		T44	237		T45	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	99562	1			T44	5		T46	4		T47	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	99786	1			T44	5		T46	4		T47	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	2941531	1			T43	5		T44	38		T46	16
bins_for_gpio_bits[27]	auto[0]	auto[0]	3354885	1			T43	40		T44	228		T45	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	99313	1			T44	4		T46	1		T47	6
bins_for_gpio_bits[27]	auto[1]	auto[0]	99567	1			T43	1		T44	5		T46	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	2943785	1			T43	9		T44	48		T46	10
bins_for_gpio_bits[28]	auto[0]	auto[0]	3368771	1			T43	45		T44	225		T45	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	99670	1			T44	8		T46	2		T47	3
bins_for_gpio_bits[28]	auto[1]	auto[0]	99917	1			T44	8		T46	2		T47	3
bins_for_gpio_bits[28]	auto[1]	auto[1]	2929192	1			T43	5		T44	44		T46	13
bins_for_gpio_bits[29]	auto[0]	auto[0]	3358429	1			T43	42		T44	201		T45	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	99520	1			T43	1		T44	9		T46	5
bins_for_gpio_bits[29]	auto[1]	auto[0]	99733	1			T43	2		T44	9		T46	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	2939868	1			T43	5		T44	66		T46	16
bins_for_gpio_bits[30]	auto[0]	auto[0]	3354405	1			T43	39		T44	240		T45	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	99778	1			T44	8		T46	5		T47	3
bins_for_gpio_bits[30]	auto[1]	auto[0]	100030	1			T43	1		T44	8		T46	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	2943337	1			T43	10		T44	29		T46	28
bins_for_gpio_bits[31]	auto[0]	auto[0]	3359154	1			T43	47		T44	220		T45	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	99631	1			T44	6		T46	3		T47	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	99865	1			T44	6		T46	3		T47	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	2938900	1			T43	3		T44	53		T46	22