Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4308030 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2264895 |
1 |
|
|
T31 |
19 |
|
T38 |
138 |
|
T39 |
211 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6282988 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
289937 |
1 |
|
|
T31 |
1 |
|
T38 |
6 |
|
T39 |
74 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4307380 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2265545 |
1 |
|
|
T31 |
25 |
|
T38 |
133 |
|
T39 |
415 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
990718 |
1 |
|
|
T31 |
14 |
|
T38 |
52 |
|
T39 |
197 |
| auto[1] |
auto[0] |
auto[1] |
144975 |
1 |
|
|
T31 |
1 |
|
T38 |
5 |
|
T39 |
45 |
| auto[1] |
auto[1] |
auto[0] |
984890 |
1 |
|
|
T31 |
10 |
|
T38 |
75 |
|
T39 |
144 |
| auto[1] |
auto[1] |
auto[1] |
144962 |
1 |
|
|
T38 |
1 |
|
T39 |
29 |
|
T70 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |