Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4333508 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2239417 |
1 |
|
|
T31 |
26 |
|
T38 |
142 |
|
T39 |
299 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6283343 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
289582 |
1 |
|
|
T38 |
5 |
|
T39 |
45 |
|
T70 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4310185 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2262740 |
1 |
|
|
T31 |
11 |
|
T38 |
120 |
|
T39 |
241 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
999471 |
1 |
|
|
T31 |
5 |
|
T38 |
46 |
|
T39 |
95 |
| auto[1] |
auto[0] |
auto[1] |
147596 |
1 |
|
|
T38 |
1 |
|
T39 |
22 |
|
T70 |
1 |
| auto[1] |
auto[1] |
auto[0] |
973687 |
1 |
|
|
T31 |
6 |
|
T38 |
69 |
|
T39 |
101 |
| auto[1] |
auto[1] |
auto[1] |
141986 |
1 |
|
|
T38 |
4 |
|
T39 |
23 |
|
T70 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |