Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4338655 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2234270 |
1 |
|
|
T31 |
32 |
|
T38 |
142 |
|
T39 |
288 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
5521989 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
1050936 |
1 |
|
|
T31 |
9 |
|
T38 |
51 |
|
T39 |
161 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4323923 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2249002 |
1 |
|
|
T31 |
13 |
|
T38 |
117 |
|
T39 |
327 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
606862 |
1 |
|
|
T38 |
37 |
|
T39 |
82 |
|
T70 |
13 |
| auto[1] |
auto[0] |
auto[1] |
531300 |
1 |
|
|
T38 |
26 |
|
T39 |
95 |
|
T70 |
11 |
| auto[1] |
auto[1] |
auto[0] |
591204 |
1 |
|
|
T31 |
4 |
|
T38 |
29 |
|
T39 |
84 |
| auto[1] |
auto[1] |
auto[1] |
519636 |
1 |
|
|
T31 |
9 |
|
T38 |
25 |
|
T39 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |