Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4305865 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2267060 |
1 |
|
|
T31 |
25 |
|
T38 |
140 |
|
T39 |
209 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6286012 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
286913 |
1 |
|
|
T31 |
1 |
|
T38 |
4 |
|
T39 |
60 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4328019 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2244906 |
1 |
|
|
T31 |
33 |
|
T38 |
140 |
|
T39 |
326 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
976649 |
1 |
|
|
T31 |
14 |
|
T38 |
62 |
|
T39 |
162 |
| auto[1] |
auto[0] |
auto[1] |
142382 |
1 |
|
|
T31 |
1 |
|
T38 |
2 |
|
T39 |
37 |
| auto[1] |
auto[1] |
auto[0] |
981344 |
1 |
|
|
T31 |
18 |
|
T38 |
74 |
|
T39 |
104 |
| auto[1] |
auto[1] |
auto[1] |
144531 |
1 |
|
|
T38 |
2 |
|
T39 |
23 |
|
T70 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |