Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4321888 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2251037 |
1 |
|
|
T31 |
12 |
|
T38 |
130 |
|
T39 |
235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6283640 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
289285 |
1 |
|
|
T38 |
4 |
|
T39 |
41 |
|
T70 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
4311252 |
1 |
|
|
T43 |
27 |
|
T44 |
143 |
|
T45 |
1 |
| auto[1] |
2261673 |
1 |
|
|
T31 |
11 |
|
T38 |
101 |
|
T39 |
268 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
988250 |
1 |
|
|
T31 |
10 |
|
T38 |
61 |
|
T39 |
152 |
| auto[1] |
auto[0] |
auto[1] |
145268 |
1 |
|
|
T38 |
2 |
|
T39 |
28 |
|
T70 |
1 |
| auto[1] |
auto[1] |
auto[0] |
984138 |
1 |
|
|
T31 |
1 |
|
T38 |
36 |
|
T39 |
75 |
| auto[1] |
auto[1] |
auto[1] |
144017 |
1 |
|
|
T38 |
2 |
|
T39 |
13 |
|
T60 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |