HMAC Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.640s	1.894ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.740s	19.009us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.830s	81.076us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.840s	2.335ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.400s	203.267us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.283m	98.832ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.830s	81.076us	20	20	100.00
		hmac_csr_aliasing	2.400s	203.267us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.081m	50.591ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.044m	6.595ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.170m	173.199ms	49	50	98.00
		hmac_test_hmac_vectors	1.300s	129.249us	50	50	100.00
V2	burst_wr	hmac_burst_wr	57.500s	17.903ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.316m	2.787ms	50	50	100.00
V2	error	hmac_error	4.212m	53.470ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.206m	18.754ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.627m	51.043ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.600s	39.855us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	22.774us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.450s	830.225us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.450s	830.225us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.740s	19.009us	5	5	100.00
		hmac_csr_rw	0.830s	81.076us	20	20	100.00
		hmac_csr_aliasing	2.400s	203.267us	5	5	100.00
		hmac_same_csr_outstanding	1.450s	285.149us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.740s	19.009us	5	5	100.00
		hmac_csr_rw	0.830s	81.076us	20	20	100.00
		hmac_csr_aliasing	2.400s	203.267us	5	5	100.00
		hmac_same_csr_outstanding	1.450s	285.149us	20	20	100.00
V2		TOTAL			589	590	99.83
V2S	tl_intg_err	hmac_sec_cm	0.880s	34.885us	5	5	100.00
		hmac_tl_intg_err	2.450s	154.868us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.450s	154.868us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.640s	1.894ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.882h	284.318ms	195	200	97.50
V3		TOTAL			195	200	97.50
		TOTAL			914	920	99.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.54	98.69	100.00	100.00	99.76	99.49	100.00

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

Test hmac_stress_all_with_rand_reset has 2 failures.

53.hmac_stress_all_with_rand_reset.4258421366
Line 300, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/53.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 22067940141 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 22067940141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

132.hmac_stress_all_with_rand_reset.705603388
Line 948, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/132.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 52351489919 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 52351489919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test hmac_test_sha_vectors has 1 failures.
  - 13.hmac_test_sha_vectors.634802447
    Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 74.hmac_stress_all_with_rand_reset.1713946796
    Line 419, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/74.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8652400498 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8652400498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 76.hmac_stress_all_with_rand_reset.3341429769
    Line 246, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/76.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1709242405 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1709242405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 134.hmac_stress_all_with_rand_reset.445162162
    Line 1448, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/134.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 104970805147 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 104970805147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```