HMAC Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.520s	801.768us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.740s	51.398us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	22.812us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	6.160s	4.052ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.280s	492.704us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.503m	89.547ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	22.812us	20	20	100.00
		hmac_csr_aliasing	2.280s	492.704us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.958m	8.732ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.048m	1.876ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.362m	46.988ms	47	50	94.00
		hmac_test_hmac_vectors	1.260s	404.416us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.209m	3.207ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.565m	11.442ms	50	50	100.00
V2	error	hmac_error	2.984m	26.932ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.369m	5.105ms	50	50	100.00
V2	stress_all	hmac_stress_all	37.913m	149.052ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.610s	13.437us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	49.630us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.180s	214.123us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.180s	214.123us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.740s	51.398us	5	5	100.00
		hmac_csr_rw	0.760s	22.812us	20	20	100.00
		hmac_csr_aliasing	2.280s	492.704us	5	5	100.00
		hmac_same_csr_outstanding	1.420s	86.027us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.740s	51.398us	5	5	100.00
		hmac_csr_rw	0.760s	22.812us	20	20	100.00
		hmac_csr_aliasing	2.280s	492.704us	5	5	100.00
		hmac_same_csr_outstanding	1.420s	86.027us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	1.030s	192.229us	5	5	100.00
		hmac_tl_intg_err	2.540s	171.646us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.540s	171.646us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.520s	801.768us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.574h	578.674ms	190	200	95.00
V3		TOTAL			190	200	95.00
		TOTAL			907	920	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.54	98.47	100.00	100.00	99.76	99.49	99.72

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 8 failures:

Test hmac_stress_all_with_rand_reset has 8 failures.

1.hmac_stress_all_with_rand_reset.1503914993
Line 1130, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 70808487439 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 70808487439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.hmac_stress_all_with_rand_reset.2108652852
Line 271, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10365688787 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 10365688787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test hmac_test_sha_vectors has 3 failures.

13.hmac_test_sha_vectors.3301150703
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.hmac_test_sha_vectors.3600388940
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 39.hmac_stress_all_with_rand_reset.1319231860
    Line 830, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/39.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 153723335024 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 153723335024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 126.hmac_stress_all_with_rand_reset.1889971746
    Line 834, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/126.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 595103797145 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 595103797145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```