HMAC Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.540s	3.106ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	141.147us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.810s	67.126us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.330s	4.059ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.300s	52.935us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	20.903m	2.111s	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.810s	67.126us	20	20	100.00
		hmac_csr_aliasing	2.300s	52.935us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.163m	89.356ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.097m	3.489ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.880m	92.182ms	48	50	96.00
		hmac_test_hmac_vectors	1.290s	77.723us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.285m	6.554ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.706m	2.981ms	50	50	100.00
V2	error	hmac_error	3.333m	12.531ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.421m	18.052ms	50	50	100.00
V2	stress_all	hmac_stress_all	38.285m	351.813ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	39.597us	50	50	100.00
V2	intr_test	hmac_intr_test	0.680s	40.939us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.590s	645.720us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.590s	645.720us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	141.147us	5	5	100.00
		hmac_csr_rw	0.810s	67.126us	20	20	100.00
		hmac_csr_aliasing	2.300s	52.935us	5	5	100.00
		hmac_same_csr_outstanding	1.550s	133.906us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	141.147us	5	5	100.00
		hmac_csr_rw	0.810s	67.126us	20	20	100.00
		hmac_csr_aliasing	2.300s	52.935us	5	5	100.00
		hmac_same_csr_outstanding	1.550s	133.906us	20	20	100.00
V2		TOTAL			588	590	99.66
V2S	tl_intg_err	hmac_sec_cm	0.880s	73.531us	5	5	100.00
		hmac_tl_intg_err	2.500s	497.126us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.500s	497.126us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.540s	3.106ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.433h	229.657ms	193	200	96.50
V3		TOTAL			193	200	96.50
		TOTAL			911	920	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.54	98.69	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 6 failures:

Test hmac_stress_all_with_rand_reset has 6 failures.

22.hmac_stress_all_with_rand_reset.2690853212
Line 1084, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 297236883501 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 297236883501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.hmac_stress_all_with_rand_reset.1774147121
Line 231, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/53.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 407603025 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 407603025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test hmac_test_sha_vectors has 2 failures.

3.hmac_test_sha_vectors.4109859182
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.hmac_test_sha_vectors.345648511
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 11.hmac_stress_all_with_rand_reset.3447124183
    Line 383, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31820626026 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 31820626026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```