HMAC Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: `877a77116`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.500s	768.137us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.710s	67.223us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.790s	23.848us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.790s	205.425us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.590s	180.974us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.178m	172.840ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.790s	23.848us	20	20	100.00
		hmac_csr_aliasing	2.590s	180.974us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.692m	20.536ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	53.500s	3.009ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.495m	41.507ms	47	50	94.00
		hmac_test_hmac_vectors	1.220s	67.067us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.266m	3.472ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.142m	2.594ms	50	50	100.00
V2	error	hmac_error	4.106m	22.811ms	49	50	98.00
V2	wipe_secret	hmac_wipe_secret	1.353m	4.671ms	50	50	100.00
V2	stress_all	hmac_stress_all	28.111m	460.918ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	87.862us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	19.637us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.720s	431.175us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.720s	431.175us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.710s	67.223us	5	5	100.00
		hmac_csr_rw	0.790s	23.848us	20	20	100.00
		hmac_csr_aliasing	2.590s	180.974us	5	5	100.00
		hmac_same_csr_outstanding	1.420s	32.535us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.710s	67.223us	5	5	100.00
		hmac_csr_rw	0.790s	23.848us	20	20	100.00
		hmac_csr_aliasing	2.590s	180.974us	5	5	100.00
		hmac_same_csr_outstanding	1.420s	32.535us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	1.080s	717.822us	5	5	100.00
		hmac_tl_intg_err	2.410s	162.655us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.410s	162.655us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.500s	768.137us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.860h	329.114ms	190	200	95.00
V3		TOTAL			190	200	95.00
		TOTAL			906	920	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.54	98.47	100.00	100.00	99.76	99.49	99.72

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 8 failures:

Test hmac_stress_all_with_rand_reset has 8 failures.

34.hmac_stress_all_with_rand_reset.4190313809
Line 407, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9203698457 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9203698457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.hmac_stress_all_with_rand_reset.3330393855
Line 1026, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/52.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49176516648 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 49176516648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test hmac_error has 1 failures.

6.hmac_error.428086184
Line 245, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test hmac_test_sha_vectors has 3 failures.

12.hmac_test_sha_vectors.224387570
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/12.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.hmac_test_sha_vectors.733127839
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 9.hmac_stress_all_with_rand_reset.1305216072
    Line 1362, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 172629245866 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 172629245866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 119.hmac_stress_all_with_rand_reset.3202484065
    Line 852, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/119.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42415588150 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 42415588150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```