Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	35563589	1			T11	1		T12	11		T13	4
all_values[1]	35563589	1			T11	1		T12	11		T13	4
all_values[2]	35563589	1			T11	1		T12	11		T13	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135186

1

T11

3

T12

19

T13

3

auto[1]

106555581

1

T12

14

T13

9

T42

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76773563

1

T11

3

T12

18

T13

10

auto[1]

29917204

1

T12

15

T13

2

T42

13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	49446	1			T11	1		T12	2		T14	1
all_values[0]	auto[0]	auto[1]	1122	1			T12	3		T42	2		T43	1
all_values[0]	auto[1]	auto[0]	35363146	1			T12	6		T13	3		T42	1
all_values[0]	auto[1]	auto[1]	149875	1			T13	1		T42	2		T43	4
all_values[1]	auto[0]	auto[0]	28528	1			T11	1		T12	5		T13	1
all_values[1]	auto[0]	auto[1]	21103	1			T12	2		T13	1		T43	3
all_values[1]	auto[1]	auto[0]	19456520	1			T12	3		T13	2		T42	2
all_values[1]	auto[1]	auto[1]	16057438	1			T12	1		T42	4		T43	3
all_values[2]	auto[0]	auto[0]	26366	1			T11	1		T12	2		T13	1
all_values[2]	auto[0]	auto[1]	8621	1			T12	5		T42	1		T94	2
all_values[2]	auto[1]	auto[0]	21849557	1			T13	3		T42	2		T43	3
all_values[2]	auto[1]	auto[1]	13679045	1			T12	4		T42	4		T43	2