Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17538152

1

T1

2856

T2

14

T3

4

auto[1]

8673656

1

T1

6649

T2

22

T3

8

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8580867

1

T1

4918

T2

16

T3

4

auto[1]

17630941

1

T1

4587

T2

20

T3

8

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15535418

1

T1

4020

T2

24

T3

6

auto[1]

10676390

1

T1

5485

T2

12

T3

6

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	15361848	1			T1	8212		T4	12263		T5	13547
fifo_depth[1]	1283784	1			T1	545		T4	692		T5	740
fifo_depth[2]	1125751	1			T1	410		T4	526		T5	717
fifo_depth[3]	937440	1			T1	228		T4	267		T5	297
fifo_depth[4]	916970	1			T1	84		T4	319		T5	348
fifo_depth[5]	772364	1			T1	20		T4	116		T5	107
fifo_depth[6]	805614	1			T1	3		T2	2		T4	103
fifo_depth[7]	680662	1			T1	3		T2	3		T3	3
fifo_depth[8]	819981	1			T2	3		T4	34		T5	140
fifo_depth[9]	476676	1			T2	3		T4	1		T5	15
fifo_depth[10]	492476	1			T2	7		T3	1		T4	2
fifo_depth[11]	300145	1			T2	7		T3	5		T9	19
fifo_depth[12]	513215	1			T5	1		T9	11		T7	73
fifo_depth[13]	230863	1			T2	2		T3	2		T9	7
fifo_depth[14]	379786	1			T2	1		T3	1		T9	3
fifo_depth[15]	216575	1			T2	2		T7	5		T8	5739
fifo_depth[16]	897658	1			T2	6		T7	1		T8	20325

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10849960

1

T1

1293

T2

36

T3

12

auto[1]

15361848

1

T1

8212

T4

12263

T5

13547

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25314150

1

T1

9505

T2

30

T3

12

auto[1]

897658

1

T2

6

T7

1

T8

20325

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

904866

1

T1

164

T2

2

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

813615

1

T1

201

T2

7

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

2822401

1

T1

86

T2

8

T4

211

auto[0]

auto[0]

auto[1]

auto[1]

887511

1

T1

103

T2

7

T3

4

auto[0]

auto[1]

auto[0]

auto[0]

1333141

1

T1

32

T2

3

T3

1

auto[0]

auto[1]

auto[0]

auto[1]

1348560

1

T1

273

T2

4

T3

1

auto[0]

auto[1]

auto[1]

auto[0]

1323016

1

T1

101

T2

1

T3

2

auto[0]

auto[1]

auto[1]

auto[1]

1416850

1

T1

333

T2

4

T3

2

auto[1]

auto[0]

auto[0]

auto[0]

811343

1

T1

1020

T4

129

T5

1119

auto[1]

auto[0]

auto[0]

auto[1]

773159

1

T1

1207

T4

1412

T5

2384

auto[1]

auto[0]

auto[1]

auto[0]

7713057

1

T1

557

T4

394

T5

1213

auto[1]

auto[0]

auto[1]

auto[1]

809466

1

T1

682

T4

961

T5

2575

auto[1]

auto[1]

auto[0]

auto[0]

1287817

1

T1

240

T4

1247

T5

1538

auto[1]

auto[1]

auto[0]

auto[1]

1308366

1

T1

1781

T4

2608

T5

1689

auto[1]

auto[1]

auto[1]

auto[0]

1342511

1

T1

656

T4

3293

T5

2652

auto[1]

auto[1]

auto[1]

auto[1]

1316129

1

T1

2069

T4

2219

T5

377

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1601042

1

T1

1184

T2

1

T3

1

auto[0]

auto[0]

auto[0]

auto[1]

1492470

1

T1

1408

T2

5

T3

1

auto[0]

auto[0]

auto[1]

auto[0]

10429721

1

T1

643

T2

7

T4

605

auto[0]

auto[0]

auto[1]

auto[1]

1586892

1

T1

785

T2

6

T3

4

auto[0]

auto[1]

auto[0]

auto[0]

2499298

1

T1

272

T2

3

T3

1

auto[0]

auto[1]

auto[0]

auto[1]

2544207

1

T1

2054

T2

4

T3

1

auto[0]

auto[1]

auto[1]

auto[0]

2543669

1

T1

757

T3

2

T4

3888

auto[0]

auto[1]

auto[1]

auto[1]

2616851

1

T1

2402

T2

4

T3

2

auto[1]

auto[0]

auto[0]

auto[0]

115167

1

T2

1

T8

4431

T27

619

auto[1]

auto[0]

auto[0]

auto[1]

94304

1

T2

2

T8

3348

T27

50

auto[1]

auto[0]

auto[1]

auto[0]

105737

1

T2

1

T8

782

T27

1325

auto[1]

auto[0]

auto[1]

auto[1]

110085

1

T2

1

T8

2229

T27

523

auto[1]

auto[1]

auto[0]

auto[0]

121660

1

T8

1426

T27

388

T28

1

auto[1]

auto[1]

auto[0]

auto[1]

112719

1

T7

1

T8

1703

T27

563

auto[1]

auto[1]

auto[1]

auto[0]

121858

1

T2

1

T8

4487

T27

2228

auto[1]

auto[1]

auto[1]

auto[1]

116128

1

T8

1919

T27

971

T29

222

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	811343	1			T1	1020		T4	129		T5	1119
fifo_depth[0]	auto[0]	auto[0]	auto[1]	773159	1			T1	1207		T4	1412		T5	2384
fifo_depth[0]	auto[0]	auto[1]	auto[0]	7713057	1			T1	557		T4	394		T5	1213
fifo_depth[0]	auto[0]	auto[1]	auto[1]	809466	1			T1	682		T4	961		T5	2575
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1287817	1			T1	240		T4	1247		T5	1538
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1308366	1			T1	1781		T4	2608		T5	1689
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1342511	1			T1	656		T4	3293		T5	2652
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1316129	1			T1	2069		T4	2219		T5	377
fifo_depth[1]	auto[0]	auto[0]	auto[0]	73377	1			T1	76		T4	6		T5	44
fifo_depth[1]	auto[0]	auto[0]	auto[1]	67023	1			T1	82		T4	52		T5	153
fifo_depth[1]	auto[0]	auto[1]	auto[0]	524609	1			T1	41		T4	28		T5	81
fifo_depth[1]	auto[0]	auto[1]	auto[1]	71036	1			T1	47		T4	52		T5	123
fifo_depth[1]	auto[1]	auto[0]	auto[0]	132261	1			T1	12		T4	81		T5	88
fifo_depth[1]	auto[1]	auto[0]	auto[1]	137076	1			T1	107		T4	152		T5	70
fifo_depth[1]	auto[1]	auto[1]	auto[0]	138705	1			T1	46		T4	195		T5	175
fifo_depth[1]	auto[1]	auto[1]	auto[1]	139697	1			T1	134		T4	126		T5	6
fifo_depth[2]	auto[0]	auto[0]	auto[0]	68118	1			T1	49		T4	7		T5	101
fifo_depth[2]	auto[0]	auto[0]	auto[1]	61540	1			T1	63		T4	52		T5	106
fifo_depth[2]	auto[0]	auto[1]	auto[0]	436693	1			T1	21		T4	39		T5	79
fifo_depth[2]	auto[0]	auto[1]	auto[1]	65784	1			T1	39		T4	39		T5	97
fifo_depth[2]	auto[1]	auto[0]	auto[0]	118465	1			T1	11		T4	48		T5	116
fifo_depth[2]	auto[1]	auto[0]	auto[1]	123901	1			T1	89		T4	96		T5	50
fifo_depth[2]	auto[1]	auto[1]	auto[0]	123242	1			T1	31		T4	143		T5	110
fifo_depth[2]	auto[1]	auto[1]	auto[1]	128008	1			T1	107		T4	102		T5	58
fifo_depth[3]	auto[0]	auto[0]	auto[0]	58465	1			T1	21		T4	1		T5	21
fifo_depth[3]	auto[0]	auto[0]	auto[1]	51767	1			T1	39		T4	21		T5	56
fifo_depth[3]	auto[0]	auto[1]	auto[0]	341076	1			T1	14		T4	33		T5	36
fifo_depth[3]	auto[0]	auto[1]	auto[1]	56217	1			T1	10		T4	14		T5	57
fifo_depth[3]	auto[1]	auto[0]	auto[0]	102909	1			T1	7		T4	22		T5	43
fifo_depth[3]	auto[1]	auto[0]	auto[1]	107763	1			T1	57		T4	46		T5	22
fifo_depth[3]	auto[1]	auto[1]	auto[0]	106574	1			T1	13		T4	70		T5	60
fifo_depth[3]	auto[1]	auto[1]	auto[1]	112669	1			T1	67		T4	60		T5	2
fifo_depth[4]	auto[0]	auto[0]	auto[0]	68995	1			T1	17		T4	21		T5	86
fifo_depth[4]	auto[0]	auto[0]	auto[1]	61324	1			T1	11		T4	31		T5	37
fifo_depth[4]	auto[0]	auto[1]	auto[0]	269054	1			T1	7		T4	50		T5	39
fifo_depth[4]	auto[0]	auto[1]	auto[1]	64824	1			T1	5		T4	31		T5	57
fifo_depth[4]	auto[1]	auto[0]	auto[0]	109595	1			T1	2		T4	28		T5	46
fifo_depth[4]	auto[1]	auto[0]	auto[1]	112740	1			T1	15		T4	23		T5	16
fifo_depth[4]	auto[1]	auto[1]	auto[0]	110205	1			T1	5		T4	100		T5	34
fifo_depth[4]	auto[1]	auto[1]	auto[1]	120233	1			T1	22		T4	35		T5	33
fifo_depth[5]	auto[0]	auto[0]	auto[0]	54950	1			T1	1		T4	3		T5	9
fifo_depth[5]	auto[0]	auto[0]	auto[1]	47510	1			T1	6		T4	10		T5	12
fifo_depth[5]	auto[0]	auto[1]	auto[0]	220155	1			T1	2		T4	25		T5	20
fifo_depth[5]	auto[0]	auto[1]	auto[1]	53466	1			T1	2		T4	6		T5	26
fifo_depth[5]	auto[1]	auto[0]	auto[0]	95008	1			T4	5		T5	16		T7	21
fifo_depth[5]	auto[1]	auto[0]	auto[1]	98359	1			T1	4		T4	9		T5	10
fifo_depth[5]	auto[1]	auto[1]	auto[0]	97878	1			T1	3		T4	34		T5	12
fifo_depth[5]	auto[1]	auto[1]	auto[1]	105038	1			T1	2		T4	24		T5	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	64483	1			T4	3		T5	29		T7	24
fifo_depth[6]	auto[0]	auto[0]	auto[1]	55612	1			T4	9		T5	27		T9	81
fifo_depth[6]	auto[0]	auto[1]	auto[0]	203058	1			T1	1		T2	1		T4	25
fifo_depth[6]	auto[0]	auto[1]	auto[1]	60809	1			T4	7		T5	30		T7	201
fifo_depth[6]	auto[1]	auto[0]	auto[0]	102973	1			T2	1		T4	10		T5	14
fifo_depth[6]	auto[1]	auto[0]	auto[1]	104274	1			T4	6		T5	12		T7	48
fifo_depth[6]	auto[1]	auto[1]	auto[0]	102751	1			T1	2		T4	31		T5	7
fifo_depth[6]	auto[1]	auto[1]	auto[1]	111654	1			T4	12		T5	10		T9	26
fifo_depth[7]	auto[0]	auto[0]	auto[0]	52934	1			T5	1		T7	20		T6	6
fifo_depth[7]	auto[0]	auto[0]	auto[1]	44918	1			T4	6		T5	21		T9	59
fifo_depth[7]	auto[0]	auto[1]	auto[0]	162818	1			T4	9		T5	12		T8	3158
fifo_depth[7]	auto[0]	auto[1]	auto[1]	51145	1			T2	1		T3	2		T4	2
fifo_depth[7]	auto[1]	auto[0]	auto[0]	88503	1			T5	7		T7	16		T8	2283
fifo_depth[7]	auto[1]	auto[0]	auto[1]	92292	1			T1	1		T2	2		T4	2
fifo_depth[7]	auto[1]	auto[1]	auto[0]	91149	1			T1	1		T4	10		T5	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	96903	1			T1	1		T3	1		T4	9
fifo_depth[8]	auto[0]	auto[0]	auto[0]	75740	1			T4	7		T5	42		T7	17
fifo_depth[8]	auto[0]	auto[0]	auto[1]	64997	1			T2	1		T4	3		T5	28
fifo_depth[8]	auto[0]	auto[1]	auto[0]	157846	1			T4	1		T5	12		T6	3
fifo_depth[8]	auto[0]	auto[1]	auto[1]	76412	1			T2	1		T4	4		T5	21
fifo_depth[8]	auto[1]	auto[0]	auto[0]	110050	1			T4	1		T5	9		T7	19
fifo_depth[8]	auto[1]	auto[0]	auto[1]	109420	1			T2	1		T5	14		T7	49
fifo_depth[8]	auto[1]	auto[1]	auto[0]	103383	1			T4	10		T5	13		T7	40
fifo_depth[8]	auto[1]	auto[1]	auto[1]	122133	1			T4	8		T5	1		T9	23
fifo_depth[9]	auto[0]	auto[0]	auto[0]	40444	1			T7	20		T8	363		T27	229
fifo_depth[9]	auto[0]	auto[0]	auto[1]	35501	1			T5	1		T9	35		T7	12
fifo_depth[9]	auto[0]	auto[1]	auto[0]	94763	1			T5	4		T8	1724		T27	871
fifo_depth[9]	auto[0]	auto[1]	auto[1]	39764	1			T2	1		T5	5		T7	124
fifo_depth[9]	auto[1]	auto[0]	auto[0]	64625	1			T2	1		T5	3		T7	11
fifo_depth[9]	auto[1]	auto[0]	auto[1]	66844	1			T7	33		T8	1404		T27	994
fifo_depth[9]	auto[1]	auto[1]	auto[0]	65283	1			T4	1		T7	35		T6	4
fifo_depth[9]	auto[1]	auto[1]	auto[1]	69452	1			T2	1		T5	2		T9	15
fifo_depth[10]	auto[0]	auto[0]	auto[0]	48413	1			T7	12		T8	609		T27	346
fifo_depth[10]	auto[0]	auto[0]	auto[1]	45290	1			T2	1		T5	4		T9	27
fifo_depth[10]	auto[0]	auto[1]	auto[0]	83788	1			T2	2		T4	1		T5	2
fifo_depth[10]	auto[0]	auto[1]	auto[1]	47547	1			T2	2		T3	1		T5	2
fifo_depth[10]	auto[1]	auto[0]	auto[0]	69064	1			T2	1		T7	5		T8	1697
fifo_depth[10]	auto[1]	auto[0]	auto[1]	65760	1			T7	33		T8	1604		T27	735
fifo_depth[10]	auto[1]	auto[1]	auto[0]	61750	1			T4	1		T7	20		T6	5
fifo_depth[10]	auto[1]	auto[1]	auto[1]	70864	1			T2	1		T5	1		T9	8
fifo_depth[11]	auto[0]	auto[0]	auto[0]	29663	1			T2	1		T7	9		T8	402
fifo_depth[11]	auto[0]	auto[0]	auto[1]	27775	1			T2	3		T3	1		T9	13
fifo_depth[11]	auto[0]	auto[1]	auto[0]	49939	1			T2	3		T8	831		T27	359
fifo_depth[11]	auto[0]	auto[1]	auto[1]	29417	1			T7	50		T8	490		T27	651
fifo_depth[11]	auto[1]	auto[0]	auto[0]	41225	1			T3	1		T7	5		T8	1226
fifo_depth[11]	auto[1]	auto[0]	auto[1]	41462	1			T7	11		T8	1136		T27	435
fifo_depth[11]	auto[1]	auto[1]	auto[0]	38738	1			T3	2		T7	18		T6	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	41926	1			T3	1		T9	6		T7	22
fifo_depth[12]	auto[0]	auto[0]	auto[0]	58607	1			T7	2		T8	1361		T27	607
fifo_depth[12]	auto[0]	auto[0]	auto[1]	56560	1			T9	9		T7	2		T8	2304
fifo_depth[12]	auto[0]	auto[1]	auto[0]	68168	1			T8	960		T27	871		T143	11
fifo_depth[12]	auto[0]	auto[1]	auto[1]	60323	1			T7	28		T8	1317		T27	666
fifo_depth[12]	auto[1]	auto[0]	auto[0]	68792	1			T5	1		T7	8		T8	1558
fifo_depth[12]	auto[1]	auto[0]	auto[1]	66194	1			T7	6		T8	2660		T27	266
fifo_depth[12]	auto[1]	auto[1]	auto[0]	60301	1			T7	5		T8	2363		T27	754
fifo_depth[12]	auto[1]	auto[1]	auto[1]	74270	1			T9	2		T7	22		T8	1134
fifo_depth[13]	auto[0]	auto[0]	auto[0]	26353	1			T3	1		T7	3		T8	330
fifo_depth[13]	auto[0]	auto[0]	auto[1]	26002	1			T9	7		T7	1		T8	922
fifo_depth[13]	auto[0]	auto[1]	auto[0]	30468	1			T2	1		T8	403		T27	234
fifo_depth[13]	auto[0]	auto[1]	auto[1]	28384	1			T3	1		T7	11		T8	541
fifo_depth[13]	auto[1]	auto[0]	auto[0]	31729	1			T7	2		T8	827		T27	75
fifo_depth[13]	auto[1]	auto[0]	auto[1]	30951	1			T7	6		T8	763		T27	174
fifo_depth[13]	auto[1]	auto[1]	auto[0]	28318	1			T7	1		T8	777		T27	613
fifo_depth[13]	auto[1]	auto[1]	auto[1]	28658	1			T2	1		T7	5		T6	1
fifo_depth[14]	auto[0]	auto[0]	auto[0]	44598	1			T7	1		T8	674		T27	533
fifo_depth[14]	auto[0]	auto[0]	auto[1]	47094	1			T9	3		T8	2173		T27	83
fifo_depth[14]	auto[0]	auto[1]	auto[0]	47683	1			T8	621		T27	685		T144	10
fifo_depth[14]	auto[0]	auto[1]	auto[1]	45566	1			T7	4		T8	1406		T27	514
fifo_depth[14]	auto[1]	auto[0]	auto[0]	48589	1			T8	881		T27	40		T143	7
fifo_depth[14]	auto[1]	auto[0]	auto[1]	49149	1			T2	1		T3	1		T7	2
fifo_depth[14]	auto[1]	auto[1]	auto[0]	45704	1			T8	1839		T27	639		T28	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	51403	1			T7	2		T8	663		T27	335
fifo_depth[15]	auto[0]	auto[0]	auto[0]	24559	1			T8	325		T27	371		T143	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	26398	1			T7	1		T8	1725		T27	61
fifo_depth[15]	auto[0]	auto[1]	auto[0]	26546	1			T8	292		T27	167		T144	4
fifo_depth[15]	auto[0]	auto[1]	auto[1]	26732	1			T2	1		T7	3		T8	857
fifo_depth[15]	auto[1]	auto[0]	auto[0]	27693	1			T8	535		T27	24		T143	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	29656	1			T8	675		T27	77		T28	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	27177	1			T8	849		T27	524		T28	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	27814	1			T2	1		T7	1		T8	481
fifo_depth[16]	auto[0]	auto[0]	auto[0]	115167	1			T2	1		T8	4431		T27	619
fifo_depth[16]	auto[0]	auto[0]	auto[1]	94304	1			T2	2		T8	3348		T27	50
fifo_depth[16]	auto[0]	auto[1]	auto[0]	105737	1			T2	1		T8	782		T27	1325
fifo_depth[16]	auto[0]	auto[1]	auto[1]	110085	1			T2	1		T8	2229		T27	523
fifo_depth[16]	auto[1]	auto[0]	auto[0]	121660	1			T8	1426		T27	388		T28	1
fifo_depth[16]	auto[1]	auto[0]	auto[1]	112719	1			T7	1		T8	1703		T27	563
fifo_depth[16]	auto[1]	auto[1]	auto[0]	121858	1			T2	1		T8	4487		T27	2228
fifo_depth[16]	auto[1]	auto[1]	auto[1]	116128	1			T8	1919		T27	971		T29	222