Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	35563589	1			T11	1		T12	11		T13	4
all_pins[1]	35563589	1			T11	1		T12	11		T13	4
all_pins[2]	35563589	1			T11	1		T12	11		T13	4

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	76610953	1			T11	3		T12	28		T13	11
values[0x1]	30079814	1			T12	5		T13	1		T42	10
transitions[0x0=>0x1]	26488485	1			T12	4		T42	3		T43	6
transitions[0x1=>0x0]	26488510	1			T12	4		T13	1		T42	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	35410305	1			T11	1		T12	11		T13	3
all_pins[0]	values[0x1]	153284	1			T13	1		T42	2		T43	4
all_pins[0]	transitions[0x0=>0x1]	153051	1			T42	1		T43	3		T95	2
all_pins[0]	transitions[0x1=>0x0]	13678837	1			T12	4		T42	3		T43	1
all_pins[1]	values[0x0]	19316104	1			T11	1		T12	10		T13	4
all_pins[1]	values[0x1]	16247485	1			T12	1		T42	4		T43	3
all_pins[1]	transitions[0x0=>0x1]	16128739	1			T12	1		T42	2		T43	1
all_pins[1]	transitions[0x1=>0x0]	34538	1			T13	1		T43	2		T68	2
all_pins[2]	values[0x0]	21884544	1			T11	1		T12	7		T13	4
all_pins[2]	values[0x1]	13679045	1			T12	4		T42	4		T43	2
all_pins[2]	transitions[0x0=>0x1]	10206695	1			T12	3		T43	2		T68	3
all_pins[2]	transitions[0x1=>0x0]	12775135	1			T43	3		T94	1		T96	2