Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3637 1 T12 10 T13 4 T42 7
all_values[1] 3637 1 T12 10 T13 4 T42 7
all_values[2] 3637 1 T12 10 T13 4 T42 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5125 1 T12 18 T13 5 T42 14
auto[1] 5786 1 T12 12 T13 7 T42 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4183 1 T12 12 T13 9 T42 5
auto[1] 6728 1 T12 18 T13 3 T42 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6290 1 T12 19 T13 10 T42 11
auto[1] 4621 1 T12 11 T13 2 T42 10


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 656 1 T12 3 T42 2 T43 3
all_values[0] auto[0] auto[0] auto[1] 337 1 T12 1 T42 1 T43 1
all_values[0] auto[0] auto[1] auto[0] 725 1 T12 4 T13 3 T94 1
all_values[0] auto[0] auto[1] auto[1] 390 1 T42 1 T43 1 T68 1
all_values[0] auto[1] auto[0] auto[1] 709 1 T12 2 T13 1 T42 3
all_values[0] auto[1] auto[1] auto[1] 820 1 T43 3 T68 2 T95 2
all_values[1] auto[0] auto[0] auto[0] 672 1 T12 3 T13 1 T42 2
all_values[1] auto[0] auto[0] auto[1] 341 1 T12 3 T13 1 T43 1
all_values[1] auto[0] auto[1] auto[0] 730 1 T12 2 T13 1 T68 2
all_values[1] auto[0] auto[1] auto[1] 343 1 T42 2 T43 1 T97 2
all_values[1] auto[1] auto[0] auto[1] 713 1 T13 1 T42 2 T43 2
all_values[1] auto[1] auto[1] auto[1] 838 1 T12 2 T42 1 T43 3
all_values[2] auto[0] auto[0] auto[0] 643 1 T13 1 T42 1 T43 3
all_values[2] auto[0] auto[0] auto[1] 338 1 T12 1 T42 1 T94 1
all_values[2] auto[0] auto[1] auto[0] 757 1 T13 3 T43 3 T96 2
all_values[2] auto[0] auto[1] auto[1] 358 1 T12 2 T42 1 T68 1
all_values[2] auto[1] auto[0] auto[1] 716 1 T12 5 T42 2 T43 1
all_values[2] auto[1] auto[1] auto[1] 825 1 T12 2 T42 2 T43 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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