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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.53 98.58 100.00 100.00 99.76 99.49 100.00


Total test records in report: 909
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T758 /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.4017438524 Dec 24 01:46:45 PM PST 23 Dec 24 01:47:24 PM PST 23 1442986288 ps
T759 /workspace/coverage/default/48.hmac_smoke.3483719319 Dec 24 01:46:19 PM PST 23 Dec 24 01:46:23 PM PST 23 149822802 ps
T760 /workspace/coverage/default/1.hmac_error.270284025 Dec 24 01:44:13 PM PST 23 Dec 24 01:45:36 PM PST 23 1337880749 ps
T761 /workspace/coverage/default/3.hmac_smoke.1213102745 Dec 24 01:44:14 PM PST 23 Dec 24 01:44:34 PM PST 23 146802048 ps
T762 /workspace/coverage/default/35.hmac_burst_wr.4179222000 Dec 24 01:45:18 PM PST 23 Dec 24 01:46:05 PM PST 23 10906466517 ps
T763 /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1290013586 Dec 24 01:46:45 PM PST 23 Dec 24 01:54:05 PM PST 23 96062588208 ps
T764 /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.305764283 Dec 24 01:46:53 PM PST 23 Dec 24 02:21:15 PM PST 23 79408087266 ps
T765 /workspace/coverage/default/21.hmac_stress_all.4243714807 Dec 24 01:46:45 PM PST 23 Dec 24 02:06:03 PM PST 23 50949744099 ps
T766 /workspace/coverage/default/31.hmac_smoke.1525434528 Dec 24 01:45:37 PM PST 23 Dec 24 01:45:41 PM PST 23 125737315 ps
T767 /workspace/coverage/default/24.hmac_burst_wr.1833768335 Dec 24 01:45:09 PM PST 23 Dec 24 01:45:48 PM PST 23 6199789371 ps
T768 /workspace/coverage/default/0.hmac_smoke.3082132569 Dec 24 01:44:13 PM PST 23 Dec 24 01:44:37 PM PST 23 700248430 ps
T769 /workspace/coverage/default/48.hmac_test_sha_vectors.2419294814 Dec 24 01:46:38 PM PST 23 Dec 24 01:52:52 PM PST 23 52117673432 ps
T770 /workspace/coverage/default/41.hmac_burst_wr.464293782 Dec 24 01:45:43 PM PST 23 Dec 24 01:45:49 PM PST 23 567616095 ps
T771 /workspace/coverage/default/11.hmac_burst_wr.727215059 Dec 24 01:45:12 PM PST 23 Dec 24 01:45:41 PM PST 23 1713046587 ps
T772 /workspace/coverage/default/40.hmac_long_msg.687557424 Dec 24 01:46:20 PM PST 23 Dec 24 01:47:12 PM PST 23 10849248699 ps
T773 /workspace/coverage/default/42.hmac_long_msg.1176701588 Dec 24 01:45:46 PM PST 23 Dec 24 01:46:21 PM PST 23 2701090855 ps
T774 /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.4240581238 Dec 24 01:45:14 PM PST 23 Dec 24 02:36:07 PM PST 23 372306609855 ps
T775 /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.3340249204 Dec 24 01:47:06 PM PST 23 Dec 24 01:50:52 PM PST 23 55937326931 ps
T776 /workspace/coverage/default/20.hmac_burst_wr.2648371738 Dec 24 01:46:37 PM PST 23 Dec 24 01:47:31 PM PST 23 1918093093 ps
T777 /workspace/coverage/default/34.hmac_error.2730645480 Dec 24 01:45:42 PM PST 23 Dec 24 01:48:22 PM PST 23 11935166687 ps
T778 /workspace/coverage/default/16.hmac_alert_test.2834250662 Dec 24 01:45:14 PM PST 23 Dec 24 01:45:21 PM PST 23 26291077 ps
T779 /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.61480396 Dec 24 01:46:45 PM PST 23 Dec 24 02:12:31 PM PST 23 466592667401 ps
T780 /workspace/coverage/default/12.hmac_test_sha_vectors.2296935940 Dec 24 01:45:10 PM PST 23 Dec 24 01:50:57 PM PST 23 6939463386 ps
T781 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2610791557 Dec 24 01:45:07 PM PST 23 Dec 24 01:48:23 PM PST 23 39788001865 ps
T782 /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2765862975 Dec 24 01:46:47 PM PST 23 Dec 24 02:05:41 PM PST 23 95383994893 ps
T783 /workspace/coverage/default/13.hmac_wipe_secret.2136567436 Dec 24 01:45:10 PM PST 23 Dec 24 01:45:31 PM PST 23 518013357 ps
T784 /workspace/coverage/default/16.hmac_test_sha_vectors.3138933342 Dec 24 01:45:12 PM PST 23 Dec 24 01:52:06 PM PST 23 126612638058 ps
T785 /workspace/coverage/default/35.hmac_test_hmac_vectors.2578966473 Dec 24 01:45:38 PM PST 23 Dec 24 01:45:41 PM PST 23 455033478 ps
T786 /workspace/coverage/default/29.hmac_error.1525726026 Dec 24 01:45:15 PM PST 23 Dec 24 01:45:35 PM PST 23 1632250119 ps
T787 /workspace/coverage/default/33.hmac_alert_test.2027989317 Dec 24 01:45:19 PM PST 23 Dec 24 01:45:26 PM PST 23 12056867 ps
T141 /workspace/coverage/default/3.hmac_wipe_secret.1045069401 Dec 24 01:44:45 PM PST 23 Dec 24 01:45:32 PM PST 23 5455588287 ps
T788 /workspace/coverage/default/24.hmac_alert_test.3490283321 Dec 24 01:45:12 PM PST 23 Dec 24 01:45:16 PM PST 23 61934969 ps
T789 /workspace/coverage/default/1.hmac_test_sha_vectors.4292253379 Dec 24 01:44:16 PM PST 23 Dec 24 01:51:48 PM PST 23 86808688949 ps
T790 /workspace/coverage/default/15.hmac_test_hmac_vectors.1655492573 Dec 24 01:45:18 PM PST 23 Dec 24 01:45:25 PM PST 23 104937673 ps
T791 /workspace/coverage/default/27.hmac_stress_all.633753145 Dec 24 01:46:04 PM PST 23 Dec 24 01:49:03 PM PST 23 6823539754 ps
T792 /workspace/coverage/default/37.hmac_test_hmac_vectors.3467680037 Dec 24 01:45:58 PM PST 23 Dec 24 01:46:03 PM PST 23 200227677 ps
T793 /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.85908996 Dec 24 01:46:45 PM PST 23 Dec 24 02:09:25 PM PST 23 349174158843 ps
T794 /workspace/coverage/default/41.hmac_back_pressure.1324118904 Dec 24 01:45:57 PM PST 23 Dec 24 01:46:37 PM PST 23 2251818017 ps
T795 /workspace/coverage/default/32.hmac_long_msg.2988327742 Dec 24 01:46:03 PM PST 23 Dec 24 01:46:19 PM PST 23 872484413 ps
T796 /workspace/coverage/default/30.hmac_smoke.2469918498 Dec 24 01:45:21 PM PST 23 Dec 24 01:45:31 PM PST 23 1089627417 ps
T797 /workspace/coverage/default/2.hmac_error.1502592038 Dec 24 01:44:16 PM PST 23 Dec 24 01:45:16 PM PST 23 882932182 ps
T798 /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3513821947 Dec 24 01:46:20 PM PST 23 Dec 24 01:59:34 PM PST 23 82933135123 ps
T799 /workspace/coverage/default/39.hmac_datapath_stress.2338255056 Dec 24 01:46:07 PM PST 23 Dec 24 01:47:10 PM PST 23 1261747079 ps
T800 /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.4162040381 Dec 24 01:45:09 PM PST 23 Dec 24 02:00:21 PM PST 23 234393852705 ps
T801 /workspace/coverage/default/15.hmac_burst_wr.1209072548 Dec 24 01:45:10 PM PST 23 Dec 24 01:45:16 PM PST 23 137183753 ps
T802 /workspace/coverage/default/17.hmac_error.2854945437 Dec 24 01:45:19 PM PST 23 Dec 24 01:48:02 PM PST 23 8589868596 ps
T803 /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.426250514 Dec 24 01:46:14 PM PST 23 Dec 24 01:47:38 PM PST 23 17029885936 ps
T804 /workspace/coverage/default/9.hmac_alert_test.194096185 Dec 24 01:46:34 PM PST 23 Dec 24 01:46:39 PM PST 23 26947264 ps
T805 /workspace/coverage/default/12.hmac_smoke.2186389344 Dec 24 01:45:14 PM PST 23 Dec 24 01:45:21 PM PST 23 515585646 ps
T806 /workspace/coverage/default/10.hmac_wipe_secret.604373306 Dec 24 01:46:41 PM PST 23 Dec 24 01:47:03 PM PST 23 390695748 ps
T807 /workspace/coverage/default/24.hmac_back_pressure.1302468023 Dec 24 01:45:13 PM PST 23 Dec 24 01:45:35 PM PST 23 1345203378 ps
T808 /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.2958814075 Dec 24 01:46:47 PM PST 23 Dec 24 01:57:57 PM PST 23 181028912028 ps
T809 /workspace/coverage/default/24.hmac_datapath_stress.3431875823 Dec 24 01:45:17 PM PST 23 Dec 24 01:45:49 PM PST 23 483383269 ps
T810 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.4052411204 Dec 24 01:46:01 PM PST 23 Dec 24 01:54:03 PM PST 23 104203556822 ps
T811 /workspace/coverage/default/21.hmac_test_hmac_vectors.965719798 Dec 24 01:45:13 PM PST 23 Dec 24 01:45:20 PM PST 23 167863228 ps
T812 /workspace/coverage/default/36.hmac_stress_all.2068049701 Dec 24 01:45:56 PM PST 23 Dec 24 02:05:56 PM PST 23 187908252998 ps
T813 /workspace/coverage/default/33.hmac_stress_all.1894164736 Dec 24 01:45:22 PM PST 23 Dec 24 01:59:37 PM PST 23 17885364160 ps
T814 /workspace/coverage/default/31.hmac_test_sha_vectors.1020812724 Dec 24 01:46:00 PM PST 23 Dec 24 01:52:01 PM PST 23 7768411554 ps
T815 /workspace/coverage/default/32.hmac_alert_test.2245270207 Dec 24 01:45:39 PM PST 23 Dec 24 01:45:41 PM PST 23 39556050 ps
T816 /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.2242876859 Dec 24 01:46:44 PM PST 23 Dec 24 01:51:59 PM PST 23 81239254764 ps
T817 /workspace/coverage/default/17.hmac_back_pressure.2733085546 Dec 24 01:45:18 PM PST 23 Dec 24 01:45:42 PM PST 23 498359189 ps
T818 /workspace/coverage/default/8.hmac_test_hmac_vectors.91294917 Dec 24 01:45:36 PM PST 23 Dec 24 01:45:38 PM PST 23 90851824 ps
T819 /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.686151500 Dec 24 01:46:45 PM PST 23 Dec 24 02:06:23 PM PST 23 914144240187 ps
T820 /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3336468790 Dec 24 01:46:35 PM PST 23 Dec 24 02:11:46 PM PST 23 337748036387 ps
T821 /workspace/coverage/default/35.hmac_stress_all.2531378503 Dec 24 01:45:25 PM PST 23 Dec 24 01:56:04 PM PST 23 53551508614 ps
T822 /workspace/coverage/default/18.hmac_stress_all.2819772228 Dec 24 01:45:15 PM PST 23 Dec 24 01:57:24 PM PST 23 301733996002 ps
T823 /workspace/coverage/default/3.hmac_stress_all.593041953 Dec 24 01:44:43 PM PST 23 Dec 24 01:49:22 PM PST 23 24713796526 ps
T824 /workspace/coverage/default/28.hmac_long_msg.3034969371 Dec 24 01:46:41 PM PST 23 Dec 24 01:49:00 PM PST 23 9334816222 ps
T825 /workspace/coverage/default/16.hmac_burst_wr.1793114518 Dec 24 01:45:19 PM PST 23 Dec 24 01:45:54 PM PST 23 1558454204 ps
T826 /workspace/coverage/default/18.hmac_test_sha_vectors.1017189831 Dec 24 01:45:12 PM PST 23 Dec 24 01:53:04 PM PST 23 40932417038 ps
T827 /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2708478718 Dec 24 01:46:45 PM PST 23 Dec 24 01:51:23 PM PST 23 74632645703 ps
T828 /workspace/coverage/default/5.hmac_test_hmac_vectors.3870696568 Dec 24 01:44:21 PM PST 23 Dec 24 01:44:37 PM PST 23 58001958 ps
T829 /workspace/coverage/default/5.hmac_alert_test.694247477 Dec 24 01:44:31 PM PST 23 Dec 24 01:44:38 PM PST 23 11388194 ps
T830 /workspace/coverage/default/12.hmac_datapath_stress.1062271008 Dec 24 01:45:17 PM PST 23 Dec 24 01:47:11 PM PST 23 25233553121 ps
T831 /workspace/coverage/default/22.hmac_back_pressure.1496437658 Dec 24 01:45:13 PM PST 23 Dec 24 01:45:38 PM PST 23 2676237043 ps
T832 /workspace/coverage/default/22.hmac_smoke.2377892838 Dec 24 01:45:12 PM PST 23 Dec 24 01:45:19 PM PST 23 71258457 ps
T833 /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.2658458050 Dec 24 01:46:52 PM PST 23 Dec 24 02:40:31 PM PST 23 516347701910 ps
T834 /workspace/coverage/default/24.hmac_test_sha_vectors.2944903076 Dec 24 01:45:18 PM PST 23 Dec 24 01:52:13 PM PST 23 24843624909 ps
T835 /workspace/coverage/default/4.hmac_error.2715830880 Dec 24 01:44:19 PM PST 23 Dec 24 01:46:03 PM PST 23 7594101022 ps
T836 /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.1926839075 Dec 24 01:46:38 PM PST 23 Dec 24 02:16:14 PM PST 23 976710632855 ps
T837 /workspace/coverage/default/48.hmac_datapath_stress.673719771 Dec 24 01:46:00 PM PST 23 Dec 24 01:46:21 PM PST 23 2120534807 ps
T838 /workspace/coverage/default/29.hmac_test_sha_vectors.4028407777 Dec 24 01:45:12 PM PST 23 Dec 24 01:52:28 PM PST 23 190983485952 ps
T839 /workspace/coverage/default/43.hmac_test_hmac_vectors.219657013 Dec 24 01:46:41 PM PST 23 Dec 24 01:46:52 PM PST 23 677384677 ps
T840 /workspace/coverage/default/14.hmac_back_pressure.2923260102 Dec 24 01:45:14 PM PST 23 Dec 24 01:45:44 PM PST 23 1470955684 ps
T841 /workspace/coverage/default/35.hmac_datapath_stress.783239848 Dec 24 01:45:20 PM PST 23 Dec 24 01:46:39 PM PST 23 7373971555 ps
T842 /workspace/coverage/default/23.hmac_stress_all.3109059755 Dec 24 01:45:13 PM PST 23 Dec 24 02:01:09 PM PST 23 19186926832 ps
T843 /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.2162289788 Dec 24 01:46:38 PM PST 23 Dec 24 02:20:06 PM PST 23 48504478273 ps
T844 /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.3239199252 Dec 24 01:46:18 PM PST 23 Dec 24 01:53:12 PM PST 23 83618422187 ps
T845 /workspace/coverage/default/36.hmac_datapath_stress.2962708905 Dec 24 01:45:43 PM PST 23 Dec 24 01:47:24 PM PST 23 3907667589 ps
T846 /workspace/coverage/default/0.hmac_datapath_stress.3549680148 Dec 24 01:44:16 PM PST 23 Dec 24 01:45:27 PM PST 23 2004305014 ps
T847 /workspace/coverage/default/42.hmac_test_sha_vectors.700170514 Dec 24 01:46:01 PM PST 23 Dec 24 01:52:50 PM PST 23 139924027393 ps
T848 /workspace/coverage/default/11.hmac_datapath_stress.1988128322 Dec 24 01:45:12 PM PST 23 Dec 24 01:45:49 PM PST 23 3288787824 ps
T849 /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.989610081 Dec 24 01:46:56 PM PST 23 Dec 24 01:54:08 PM PST 23 173976568383 ps
T850 /workspace/coverage/default/14.hmac_burst_wr.820418748 Dec 24 01:45:13 PM PST 23 Dec 24 01:45:31 PM PST 23 1025897284 ps
T851 /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.1251995021 Dec 24 01:46:43 PM PST 23 Dec 24 02:21:03 PM PST 23 1112526863313 ps
T852 /workspace/coverage/default/10.hmac_datapath_stress.444018396 Dec 24 01:46:00 PM PST 23 Dec 24 01:46:33 PM PST 23 2055879976 ps
T853 /workspace/coverage/default/38.hmac_burst_wr.3477304032 Dec 24 01:46:01 PM PST 23 Dec 24 01:46:30 PM PST 23 6418019018 ps
T854 /workspace/coverage/default/31.hmac_alert_test.239225980 Dec 24 01:45:58 PM PST 23 Dec 24 01:46:01 PM PST 23 12848925 ps
T855 /workspace/coverage/default/34.hmac_alert_test.3153897339 Dec 24 01:45:16 PM PST 23 Dec 24 01:45:24 PM PST 23 77580783 ps
T856 /workspace/coverage/default/39.hmac_burst_wr.3417139061 Dec 24 01:46:09 PM PST 23 Dec 24 01:46:42 PM PST 23 1836550661 ps
T857 /workspace/coverage/default/15.hmac_alert_test.1185364059 Dec 24 01:45:09 PM PST 23 Dec 24 01:45:12 PM PST 23 79283544 ps
T858 /workspace/coverage/default/30.hmac_long_msg.542493816 Dec 24 01:45:41 PM PST 23 Dec 24 01:47:09 PM PST 23 20964795529 ps
T859 /workspace/coverage/default/22.hmac_long_msg.3813676680 Dec 24 01:45:13 PM PST 23 Dec 24 01:46:35 PM PST 23 8698145702 ps
T860 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.976899398 Dec 24 12:31:57 PM PST 23 Dec 24 12:32:27 PM PST 23 64323220 ps
T861 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2744794322 Dec 24 12:34:06 PM PST 23 Dec 24 12:34:45 PM PST 23 87365912 ps
T104 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3837815793 Dec 24 12:31:17 PM PST 23 Dec 24 12:31:41 PM PST 23 401003688 ps
T862 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2866123656 Dec 24 12:31:39 PM PST 23 Dec 24 12:32:07 PM PST 23 41422501 ps
T83 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.608928751 Dec 24 12:31:23 PM PST 23 Dec 24 12:31:49 PM PST 23 115748154 ps
T84 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.861670730 Dec 24 12:33:38 PM PST 23 Dec 24 12:34:17 PM PST 23 192000580 ps
T863 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1883100526 Dec 24 12:31:58 PM PST 23 Dec 24 12:32:25 PM PST 23 31999288 ps
T864 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1498665168 Dec 24 12:31:48 PM PST 23 Dec 24 12:32:19 PM PST 23 18184667 ps
T865 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3702252681 Dec 24 12:31:58 PM PST 23 Dec 24 12:32:25 PM PST 23 11262046 ps
T866 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3438284595 Dec 24 12:31:29 PM PST 23 Dec 24 12:31:55 PM PST 23 16991319 ps
T85 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.248274824 Dec 24 12:31:59 PM PST 23 Dec 24 12:32:26 PM PST 23 71657465 ps
T867 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1245122985 Dec 24 12:33:42 PM PST 23 Dec 24 12:34:20 PM PST 23 51009510 ps
T868 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3312870389 Dec 24 12:34:00 PM PST 23 Dec 24 12:34:39 PM PST 23 34119203 ps
T86 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3618215146 Dec 24 12:31:29 PM PST 23 Dec 24 12:32:00 PM PST 23 595657376 ps
T869 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2336399920 Dec 24 12:31:38 PM PST 23 Dec 24 12:32:05 PM PST 23 18255154 ps
T870 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3900315462 Dec 24 12:31:44 PM PST 23 Dec 24 12:36:00 PM PST 23 161459098621 ps
T871 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2553500127 Dec 24 12:31:46 PM PST 23 Dec 24 12:32:15 PM PST 23 14233748 ps
T872 /workspace/coverage/cover_reg_top/11.hmac_intr_test.389650321 Dec 24 12:32:15 PM PST 23 Dec 24 12:32:40 PM PST 23 67419506 ps
T873 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3095370730 Dec 24 12:31:51 PM PST 23 Dec 24 12:32:21 PM PST 23 17606152 ps
T874 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1857624615 Dec 24 12:31:38 PM PST 23 Dec 24 12:32:05 PM PST 23 171807264 ps
T875 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2164579476 Dec 24 12:31:45 PM PST 23 Dec 24 12:32:14 PM PST 23 16525752 ps
T87 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1205106222 Dec 24 12:31:44 PM PST 23 Dec 24 12:32:13 PM PST 23 21840894 ps
T876 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1868762648 Dec 24 12:31:36 PM PST 23 Dec 24 12:32:02 PM PST 23 15331255 ps
T877 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3623512381 Dec 24 12:31:47 PM PST 23 Dec 24 12:32:16 PM PST 23 24079094 ps
T878 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2150448239 Dec 24 12:31:33 PM PST 23 Dec 24 12:32:01 PM PST 23 657315182 ps
T879 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1429282591 Dec 24 12:31:37 PM PST 23 Dec 24 12:32:02 PM PST 23 52409922 ps
T880 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1802040845 Dec 24 12:31:35 PM PST 23 Dec 24 12:32:01 PM PST 23 137490870 ps
T881 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4229719574 Dec 24 12:32:05 PM PST 23 Dec 24 12:32:31 PM PST 23 40124295 ps
T882 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1917631615 Dec 24 12:31:24 PM PST 23 Dec 24 12:31:51 PM PST 23 462998332 ps
T883 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1320027039 Dec 24 12:31:39 PM PST 23 Dec 24 12:32:07 PM PST 23 80216306 ps
T884 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3705542786 Dec 24 12:31:16 PM PST 23 Dec 24 12:31:40 PM PST 23 205214962 ps
T885 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1728025131 Dec 24 12:31:29 PM PST 23 Dec 24 12:31:55 PM PST 23 152195628 ps
T886 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2690194184 Dec 24 12:31:34 PM PST 23 Dec 24 12:32:00 PM PST 23 15332820 ps
T887 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2022701899 Dec 24 12:31:55 PM PST 23 Dec 24 12:32:25 PM PST 23 187220315 ps
T888 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.830507200 Dec 24 12:32:02 PM PST 23 Dec 24 12:32:30 PM PST 23 43450286 ps
T889 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3664454173 Dec 24 12:31:51 PM PST 23 Dec 24 12:32:21 PM PST 23 43285021 ps
T890 /workspace/coverage/cover_reg_top/4.hmac_intr_test.180946213 Dec 24 12:31:22 PM PST 23 Dec 24 12:31:48 PM PST 23 39262521 ps
T891 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2323260396 Dec 24 12:32:05 PM PST 23 Dec 24 12:32:33 PM PST 23 838976657 ps
T892 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1830207356 Dec 24 12:34:00 PM PST 23 Dec 24 12:34:39 PM PST 23 24387241 ps
T893 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.787253638 Dec 24 12:32:00 PM PST 23 Dec 24 12:32:27 PM PST 23 65587587 ps
T894 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2754703220 Dec 24 12:31:50 PM PST 23 Dec 24 12:32:20 PM PST 23 36756677 ps
T895 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1689373859 Dec 24 12:31:21 PM PST 23 Dec 24 12:31:47 PM PST 23 14942573 ps
T896 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3709584926 Dec 24 12:31:32 PM PST 23 Dec 24 12:31:58 PM PST 23 49129482 ps
T897 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1555522614 Dec 24 12:31:28 PM PST 23 Dec 24 12:31:54 PM PST 23 44795235 ps
T898 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2869344753 Dec 24 12:32:06 PM PST 23 Dec 24 12:32:33 PM PST 23 36352857 ps
T899 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2409265810 Dec 24 12:32:13 PM PST 23 Dec 24 12:32:41 PM PST 23 415671870 ps
T900 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2928238139 Dec 24 12:31:15 PM PST 23 Dec 24 12:31:38 PM PST 23 24151011 ps
T901 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4207028288 Dec 24 12:31:51 PM PST 23 Dec 24 12:32:21 PM PST 23 64545065 ps
T902 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2246556089 Dec 24 12:31:19 PM PST 23 Dec 24 12:31:44 PM PST 23 44851380 ps
T903 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2794266420 Dec 24 12:31:27 PM PST 23 Dec 24 12:31:53 PM PST 23 15227985 ps
T904 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.50807160 Dec 24 12:31:23 PM PST 23 Dec 24 12:31:52 PM PST 23 57376026 ps
T905 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.841531845 Dec 24 12:31:26 PM PST 23 Dec 24 12:43:04 PM PST 23 52010264054 ps
T906 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2604990769 Dec 24 12:32:07 PM PST 23 Dec 24 12:32:34 PM PST 23 463869346 ps
T907 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2839814933 Dec 24 12:31:33 PM PST 23 Dec 24 12:31:59 PM PST 23 23498934 ps
T908 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4042784507 Dec 24 12:31:46 PM PST 23 Dec 24 12:32:16 PM PST 23 23196349 ps
T909 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.909441851 Dec 24 12:31:33 PM PST 23 Dec 24 12:32:00 PM PST 23 31686913 ps

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3429306803
Short name T11
Test name
Test status
Simulation time 148135251 ps
CPU time 2.03 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:34:11 PM PST 23
Peak memory 198084 kb
Host smart-b42c3a07-ecd8-4059-af44-d3e3db52362e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429306803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3429306803
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.4057498455
Short name T8
Test name
Test status
Simulation time 465505763557 ps
CPU time 4060.4 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 02:53:01 PM PST 23
Peak memory 248036 kb
Host smart-236a3591-ca96-4196-8a7f-342849b40492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057498455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.4057498455
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.261901335
Short name T18
Test name
Test status
Simulation time 413078376425 ps
CPU time 918.13 seconds
Started Dec 24 12:31:31 PM PST 23
Finished Dec 24 12:47:14 PM PST 23
Peak memory 219144 kb
Host smart-09bf95ee-f86d-42aa-8d85-7c5a1d53c9cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261901335 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.261901335
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3047200227
Short name T42
Test name
Test status
Simulation time 12586233 ps
CPU time 0.56 seconds
Started Dec 24 12:31:35 PM PST 23
Finished Dec 24 12:32:01 PM PST 23
Peak memory 183576 kb
Host smart-8a0ddf92-880a-43a1-8f85-8cadfb9b1e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047200227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3047200227
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.841072005
Short name T41
Test name
Test status
Simulation time 43521336 ps
CPU time 1.14 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:32:14 PM PST 23
Peak memory 197780 kb
Host smart-8db6923b-38b7-48ed-8669-eff938a0af23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841072005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.841072005
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3058868861
Short name T15
Test name
Test status
Simulation time 44578795 ps
CPU time 0.73 seconds
Started Dec 24 12:31:48 PM PST 23
Finished Dec 24 12:32:17 PM PST 23
Peak memory 194700 kb
Host smart-52ac192a-647f-4a6d-8b22-5234ccf1bbed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058868861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3058868861
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.811129860
Short name T27
Test name
Test status
Simulation time 46271103580 ps
CPU time 2108.87 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 02:20:28 PM PST 23
Peak memory 248064 kb
Host smart-bb824809-0afe-4405-ae8d-af270bf8b2e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811129860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.811129860
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1101457203
Short name T44
Test name
Test status
Simulation time 62782543 ps
CPU time 0.8 seconds
Started Dec 24 01:44:39 PM PST 23
Finished Dec 24 01:44:41 PM PST 23
Peak memory 215860 kb
Host smart-af61c0aa-ad11-49e1-ba9b-f1a47e8cc0a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101457203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1101457203
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1444006592
Short name T43
Test name
Test status
Simulation time 16541220 ps
CPU time 0.57 seconds
Started Dec 24 12:31:41 PM PST 23
Finished Dec 24 12:32:09 PM PST 23
Peak memory 183516 kb
Host smart-1ae682cd-0aa8-46c7-8378-ce68961901b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444006592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1444006592
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.129681167
Short name T132
Test name
Test status
Simulation time 30516477827 ps
CPU time 1254.87 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 02:07:45 PM PST 23
Peak memory 245984 kb
Host smart-dcaac8e7-f0e6-47a1-8f24-ab4c3944ef87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129681167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.129681167
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.250118639
Short name T56
Test name
Test status
Simulation time 629003524 ps
CPU time 2.22 seconds
Started Dec 24 12:33:09 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 196992 kb
Host smart-78b03927-cfdc-493b-bed7-a4b08f7c36d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250118639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.250118639
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.246460276
Short name T334
Test name
Test status
Simulation time 63478373700 ps
CPU time 1206.61 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 223456 kb
Host smart-3b86dad9-82ed-4627-ad06-b15e3b42fc5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246460276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.246460276
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2387999328
Short name T40
Test name
Test status
Simulation time 13328393 ps
CPU time 0.58 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:45:27 PM PST 23
Peak memory 191916 kb
Host smart-9b28f9b9-560a-4d24-9b45-def82b5972d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387999328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2387999328
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2719854924
Short name T101
Test name
Test status
Simulation time 394797298 ps
CPU time 1.75 seconds
Started Dec 24 12:31:35 PM PST 23
Finished Dec 24 12:32:01 PM PST 23
Peak memory 198064 kb
Host smart-b5a093aa-f39b-429f-b389-637ef6d946c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719854924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2719854924
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1354795623
Short name T160
Test name
Test status
Simulation time 16572016 ps
CPU time 0.56 seconds
Started Dec 24 12:32:01 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 183568 kb
Host smart-49ebe6ba-4452-40bb-b268-a3149eff2aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354795623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1354795623
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.1203258211
Short name T134
Test name
Test status
Simulation time 644369438512 ps
CPU time 2283.32 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 02:24:24 PM PST 23
Peak memory 249064 kb
Host smart-23ff483c-4125-49f6-8c35-9a4bb88f392c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203258211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.1203258211
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1989865230
Short name T121
Test name
Test status
Simulation time 428990472326 ps
CPU time 2044.46 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 02:20:55 PM PST 23
Peak memory 253740 kb
Host smart-166fc15e-a700-40d2-8a2f-65a223b3c620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989865230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1989865230
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.30426189
Short name T99
Test name
Test status
Simulation time 122270853 ps
CPU time 1.77 seconds
Started Dec 24 12:31:56 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 198024 kb
Host smart-f56c2095-2e4c-4200-9365-f6e14b6d044e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30426189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.30426189
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.470442043
Short name T508
Test name
Test status
Simulation time 884908306673 ps
CPU time 1797.84 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:16:50 PM PST 23
Peak memory 245428 kb
Host smart-31678895-e14b-46e4-be99-ba9ce2909d9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470442043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.470442043
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.3845440088
Short name T131
Test name
Test status
Simulation time 31851382513 ps
CPU time 1431.69 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:10:44 PM PST 23
Peak memory 243252 kb
Host smart-cf7ab2c5-0224-408d-bac0-2ae15ba793af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3845440088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.3845440088
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3507169169
Short name T128
Test name
Test status
Simulation time 31796819389 ps
CPU time 112.89 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:47:17 PM PST 23
Peak memory 198836 kb
Host smart-ab9a2a11-63dc-4336-81d2-3831187b08c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507169169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3507169169
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2415420074
Short name T140
Test name
Test status
Simulation time 203916914698 ps
CPU time 2179.23 seconds
Started Dec 24 01:44:42 PM PST 23
Finished Dec 24 02:21:02 PM PST 23
Peak memory 239104 kb
Host smart-b0fd9eda-c673-46f1-9106-2028508ce7c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415420074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2415420074
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1903508787
Short name T59
Test name
Test status
Simulation time 334496477 ps
CPU time 2.54 seconds
Started Dec 24 12:31:23 PM PST 23
Finished Dec 24 12:31:51 PM PST 23
Peak memory 198164 kb
Host smart-e213d7a8-4c71-4d05-8ba8-c37fa0ba369e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903508787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1903508787
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4122028853
Short name T195
Test name
Test status
Simulation time 186922768 ps
CPU time 2.63 seconds
Started Dec 24 12:31:43 PM PST 23
Finished Dec 24 12:32:13 PM PST 23
Peak memory 192000 kb
Host smart-c1951ec3-7452-4f1e-8776-27a70dd978fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122028853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4122028853
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2078943965
Short name T81
Test name
Test status
Simulation time 1331479806 ps
CPU time 6.29 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:32:05 PM PST 23
Peak memory 192048 kb
Host smart-729487dd-ede4-47ff-ac4a-17d5abca7ffe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078943965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2078943965
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2928238139
Short name T900
Test name
Test status
Simulation time 24151011 ps
CPU time 0.7 seconds
Started Dec 24 12:31:15 PM PST 23
Finished Dec 24 12:31:38 PM PST 23
Peak memory 194184 kb
Host smart-bd98ee73-065a-44a9-b3d9-b2d9b35e44a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928238139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2928238139
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1857624615
Short name T874
Test name
Test status
Simulation time 171807264 ps
CPU time 0.89 seconds
Started Dec 24 12:31:38 PM PST 23
Finished Dec 24 12:32:05 PM PST 23
Peak memory 198320 kb
Host smart-43232353-c61e-43c0-8cdf-140b08766b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857624615 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1857624615
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4207028288
Short name T901
Test name
Test status
Simulation time 64545065 ps
CPU time 0.7 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:21 PM PST 23
Peak memory 193928 kb
Host smart-e049d440-8359-4cc9-a1f5-cba2bd516f86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207028288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4207028288
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2653772428
Short name T146
Test name
Test status
Simulation time 13467858 ps
CPU time 0.59 seconds
Started Dec 24 12:31:36 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 183568 kb
Host smart-6e3d0620-17f8-4e3d-a842-8a98d5bb0ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653772428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2653772428
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3438284595
Short name T866
Test name
Test status
Simulation time 16991319 ps
CPU time 0.76 seconds
Started Dec 24 12:31:29 PM PST 23
Finished Dec 24 12:31:55 PM PST 23
Peak memory 195056 kb
Host smart-94161d97-2a79-4adf-919b-1548f53890a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438284595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3438284595
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2150448239
Short name T878
Test name
Test status
Simulation time 657315182 ps
CPU time 2.78 seconds
Started Dec 24 12:31:33 PM PST 23
Finished Dec 24 12:32:01 PM PST 23
Peak memory 198420 kb
Host smart-ecd4fa50-4fba-4baf-97c8-3d38f08d347e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150448239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2150448239
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.351898934
Short name T157
Test name
Test status
Simulation time 209423196 ps
CPU time 1.27 seconds
Started Dec 24 12:31:45 PM PST 23
Finished Dec 24 12:32:14 PM PST 23
Peak memory 195332 kb
Host smart-40aacaa4-da62-43a8-b7dd-bf7e1ded22af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351898934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.351898934
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3822674940
Short name T176
Test name
Test status
Simulation time 451857614 ps
CPU time 6.3 seconds
Started Dec 24 12:31:30 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 191964 kb
Host smart-e396a063-954a-4963-9bc4-12dd598c6c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822674940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3822674940
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1602999706
Short name T189
Test name
Test status
Simulation time 64156808 ps
CPU time 0.66 seconds
Started Dec 24 12:31:33 PM PST 23
Finished Dec 24 12:31:59 PM PST 23
Peak memory 193836 kb
Host smart-0e61c54c-84a6-4338-abf2-49f7cb944a28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602999706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1602999706
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4018407475
Short name T156
Test name
Test status
Simulation time 20345782 ps
CPU time 0.99 seconds
Started Dec 24 12:33:54 PM PST 23
Finished Dec 24 12:34:32 PM PST 23
Peak memory 197320 kb
Host smart-3bb9fb56-851c-411f-8ae3-f353f37bcc53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018407475 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4018407475
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.608928751
Short name T83
Test name
Test status
Simulation time 115748154 ps
CPU time 0.71 seconds
Started Dec 24 12:31:23 PM PST 23
Finished Dec 24 12:31:49 PM PST 23
Peak memory 194584 kb
Host smart-b3e4fe97-7077-4808-823f-9a39f9fe0acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608928751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.608928751
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1689373859
Short name T895
Test name
Test status
Simulation time 14942573 ps
CPU time 0.57 seconds
Started Dec 24 12:31:21 PM PST 23
Finished Dec 24 12:31:47 PM PST 23
Peak memory 183560 kb
Host smart-a82593ea-c3cf-4162-b9e7-692abc622c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689373859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1689373859
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1058579004
Short name T20
Test name
Test status
Simulation time 180392638 ps
CPU time 1.08 seconds
Started Dec 24 12:31:19 PM PST 23
Finished Dec 24 12:31:44 PM PST 23
Peak memory 191984 kb
Host smart-f2d27e0d-76b9-4b61-a14e-c60ab28ab0ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058579004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1058579004
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1054524488
Short name T25
Test name
Test status
Simulation time 94192343 ps
CPU time 1.27 seconds
Started Dec 24 12:31:21 PM PST 23
Finished Dec 24 12:31:47 PM PST 23
Peak memory 198352 kb
Host smart-54ad6d73-787c-4410-bcf1-b73e407e34cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054524488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1054524488
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3490680508
Short name T57
Test name
Test status
Simulation time 239664140 ps
CPU time 1.68 seconds
Started Dec 24 12:31:24 PM PST 23
Finished Dec 24 12:31:51 PM PST 23
Peak memory 198156 kb
Host smart-bdce962c-ef8c-49a1-afde-c72cf65fe7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490680508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3490680508
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2508985097
Short name T193
Test name
Test status
Simulation time 49847210 ps
CPU time 1.81 seconds
Started Dec 24 12:31:48 PM PST 23
Finished Dec 24 12:32:20 PM PST 23
Peak memory 198552 kb
Host smart-3f725ff4-7f5f-40e9-b2a9-52438b387904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508985097 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2508985097
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2393679864
Short name T75
Test name
Test status
Simulation time 82898128 ps
CPU time 0.71 seconds
Started Dec 24 12:31:26 PM PST 23
Finished Dec 24 12:31:52 PM PST 23
Peak memory 194280 kb
Host smart-df5d261e-2aae-403c-b7f6-6ad7d40d70f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393679864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2393679864
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3167091759
Short name T177
Test name
Test status
Simulation time 12031424 ps
CPU time 0.61 seconds
Started Dec 24 12:31:32 PM PST 23
Finished Dec 24 12:31:58 PM PST 23
Peak memory 183652 kb
Host smart-12bdaf8c-d3e5-42b4-8574-8c9b8e7b1ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167091759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3167091759
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1555485163
Short name T192
Test name
Test status
Simulation time 219099790 ps
CPU time 1.25 seconds
Started Dec 24 12:31:16 PM PST 23
Finished Dec 24 12:31:39 PM PST 23
Peak memory 196732 kb
Host smart-c4e3ed26-4fdf-4a51-9a13-9408a7969ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555485163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1555485163
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3858784528
Short name T65
Test name
Test status
Simulation time 60830293 ps
CPU time 1.54 seconds
Started Dec 24 12:31:47 PM PST 23
Finished Dec 24 12:32:17 PM PST 23
Peak memory 198524 kb
Host smart-51ced3cb-0f81-4bec-9fa7-66ba167d632e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858784528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3858784528
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.4047680242
Short name T98
Test name
Test status
Simulation time 1425050829 ps
CPU time 2.4 seconds
Started Dec 24 12:33:38 PM PST 23
Finished Dec 24 12:34:16 PM PST 23
Peak memory 197876 kb
Host smart-7a4b4b8a-6610-48a6-b565-1af8e2a87235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047680242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4047680242
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1058222223
Short name T145
Test name
Test status
Simulation time 20429346 ps
CPU time 1.46 seconds
Started Dec 24 12:31:29 PM PST 23
Finished Dec 24 12:31:55 PM PST 23
Peak memory 198480 kb
Host smart-2ce7fd3a-9d2e-4445-afd7-e892310bfae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058222223 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1058222223
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2323638641
Short name T70
Test name
Test status
Simulation time 11127982 ps
CPU time 0.59 seconds
Started Dec 24 12:31:25 PM PST 23
Finished Dec 24 12:31:51 PM PST 23
Peak memory 193896 kb
Host smart-54f6af8e-02cd-4c0b-9228-67156b385144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323638641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2323638641
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.389650321
Short name T872
Test name
Test status
Simulation time 67419506 ps
CPU time 0.55 seconds
Started Dec 24 12:32:15 PM PST 23
Finished Dec 24 12:32:40 PM PST 23
Peak memory 183636 kb
Host smart-26e73367-0086-4b00-a3bb-07215e164bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389650321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.389650321
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1408695407
Short name T16
Test name
Test status
Simulation time 324559218 ps
CPU time 1.31 seconds
Started Dec 24 12:32:03 PM PST 23
Finished Dec 24 12:32:30 PM PST 23
Peak memory 191968 kb
Host smart-b8c4e6f8-8525-4dbc-8be5-7cd7c81975ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408695407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1408695407
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1245122985
Short name T867
Test name
Test status
Simulation time 51009510 ps
CPU time 2.62 seconds
Started Dec 24 12:33:42 PM PST 23
Finished Dec 24 12:34:20 PM PST 23
Peak memory 198136 kb
Host smart-8b4f046f-bb3f-4a99-bed2-58a20a695732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245122985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1245122985
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3235292880
Short name T163
Test name
Test status
Simulation time 553682796 ps
CPU time 2.35 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 198328 kb
Host smart-6dab20fc-1656-46d3-ae53-d288473d0946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235292880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3235292880
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1498665168
Short name T864
Test name
Test status
Simulation time 18184667 ps
CPU time 1.02 seconds
Started Dec 24 12:31:48 PM PST 23
Finished Dec 24 12:32:19 PM PST 23
Peak memory 198272 kb
Host smart-27d0f156-ecda-498a-b2e8-640e9ed4cbc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498665168 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1498665168
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.248274824
Short name T85
Test name
Test status
Simulation time 71657465 ps
CPU time 0.69 seconds
Started Dec 24 12:31:59 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 194464 kb
Host smart-b9524eb5-b53d-4791-9de5-ad1ec19280cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248274824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.248274824
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.317064056
Short name T196
Test name
Test status
Simulation time 12597167 ps
CPU time 0.56 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 183656 kb
Host smart-38b17fc6-8f78-488b-8196-0b3a8a97a9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317064056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.317064056
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4176694810
Short name T175
Test name
Test status
Simulation time 43238382 ps
CPU time 1.12 seconds
Started Dec 24 12:32:54 PM PST 23
Finished Dec 24 12:33:34 PM PST 23
Peak memory 191040 kb
Host smart-fce176a1-2ae7-47bc-aa0f-c71c812bd395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176694810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.4176694810
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.472060049
Short name T188
Test name
Test status
Simulation time 145808342 ps
CPU time 2.04 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:05 PM PST 23
Peak memory 198420 kb
Host smart-d2086416-8f92-436a-b1f4-7ef25327329f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472060049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.472060049
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3423009799
Short name T103
Test name
Test status
Simulation time 368281166 ps
CPU time 2.11 seconds
Started Dec 24 12:31:35 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 198112 kb
Host smart-e8981164-02e2-49ee-8645-7a019694d09b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423009799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3423009799
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.841531845
Short name T905
Test name
Test status
Simulation time 52010264054 ps
CPU time 671.43 seconds
Started Dec 24 12:31:26 PM PST 23
Finished Dec 24 12:43:04 PM PST 23
Peak memory 206176 kb
Host smart-baf6aa10-ab0c-4b21-8880-b2469d7a8397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841531845 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.841531845
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1700013093
Short name T78
Test name
Test status
Simulation time 48257289 ps
CPU time 0.73 seconds
Started Dec 24 12:31:43 PM PST 23
Finished Dec 24 12:32:11 PM PST 23
Peak memory 194656 kb
Host smart-c89ed3f3-64a9-461d-b826-75062d52b813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700013093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1700013093
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3860651501
Short name T153
Test name
Test status
Simulation time 26026236 ps
CPU time 0.55 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:21 PM PST 23
Peak memory 183676 kb
Host smart-67c3b065-0ff0-4a7a-aebe-839454dce1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860651501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3860651501
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4042784507
Short name T908
Test name
Test status
Simulation time 23196349 ps
CPU time 1.01 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:16 PM PST 23
Peak memory 192044 kb
Host smart-f3c56e2f-d397-4f5d-972e-575ffbcb7426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042784507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4042784507
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1802040845
Short name T880
Test name
Test status
Simulation time 137490870 ps
CPU time 1.69 seconds
Started Dec 24 12:31:35 PM PST 23
Finished Dec 24 12:32:01 PM PST 23
Peak memory 198436 kb
Host smart-06db9d1b-cb95-4d87-ba38-2560e56ae678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802040845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1802040845
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3900315462
Short name T870
Test name
Test status
Simulation time 161459098621 ps
CPU time 228.04 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:36:00 PM PST 23
Peak memory 208456 kb
Host smart-5b62670a-cbdd-4f88-8a7b-d8ca4379c21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900315462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3900315462
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3709584926
Short name T896
Test name
Test status
Simulation time 49129482 ps
CPU time 0.65 seconds
Started Dec 24 12:31:32 PM PST 23
Finished Dec 24 12:31:58 PM PST 23
Peak memory 194052 kb
Host smart-7eb5090d-6bbd-416c-91da-4e9b262a343a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709584926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3709584926
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3702252681
Short name T865
Test name
Test status
Simulation time 11262046 ps
CPU time 0.56 seconds
Started Dec 24 12:31:58 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 183676 kb
Host smart-4592363c-6658-4bf4-9405-25543fea2d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702252681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3702252681
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.861129296
Short name T92
Test name
Test status
Simulation time 238568936 ps
CPU time 1.06 seconds
Started Dec 24 12:31:42 PM PST 23
Finished Dec 24 12:32:10 PM PST 23
Peak memory 196784 kb
Host smart-bf7c3642-7aab-48e1-8a29-270121646336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861129296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.861129296
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2022701899
Short name T887
Test name
Test status
Simulation time 187220315 ps
CPU time 1.25 seconds
Started Dec 24 12:31:55 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 198444 kb
Host smart-353ae9ad-cf50-4186-b4f0-134d9d7ffbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022701899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2022701899
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3705542786
Short name T884
Test name
Test status
Simulation time 205214962 ps
CPU time 1.07 seconds
Started Dec 24 12:31:16 PM PST 23
Finished Dec 24 12:31:40 PM PST 23
Peak memory 197876 kb
Host smart-fe3274b8-97cb-4b50-9d06-56dd95366309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705542786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3705542786
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1868762648
Short name T876
Test name
Test status
Simulation time 15331255 ps
CPU time 0.87 seconds
Started Dec 24 12:31:36 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 198220 kb
Host smart-2a7a5736-f504-45cd-a61e-3e374610c79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868762648 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1868762648
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2690194184
Short name T886
Test name
Test status
Simulation time 15332820 ps
CPU time 0.63 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 193784 kb
Host smart-2bb40c27-ce74-4687-a657-329859b6f900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690194184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2690194184
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2839814933
Short name T907
Test name
Test status
Simulation time 23498934 ps
CPU time 0.58 seconds
Started Dec 24 12:31:33 PM PST 23
Finished Dec 24 12:31:59 PM PST 23
Peak memory 183676 kb
Host smart-eb24d336-ef1b-4203-8629-c9ecc7a3018e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839814933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2839814933
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3730845094
Short name T161
Test name
Test status
Simulation time 41783395 ps
CPU time 0.79 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:21 PM PST 23
Peak memory 195204 kb
Host smart-14132bc6-513c-4283-b347-57667e738398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730845094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3730845094
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2326791580
Short name T14
Test name
Test status
Simulation time 95297527 ps
CPU time 2.61 seconds
Started Dec 24 12:31:28 PM PST 23
Finished Dec 24 12:31:56 PM PST 23
Peak memory 198588 kb
Host smart-4677f5b2-a82d-461b-a8d2-0578387529ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326791580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2326791580
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.439038178
Short name T191
Test name
Test status
Simulation time 171433084 ps
CPU time 2.38 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:17 PM PST 23
Peak memory 198204 kb
Host smart-a0ec4f05-e967-458f-8708-c432b68ec84a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439038178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.439038178
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.976899398
Short name T860
Test name
Test status
Simulation time 64323220 ps
CPU time 2.09 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 198504 kb
Host smart-fb8b08ff-8aad-40fa-857a-d1602374c554
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976899398 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.976899398
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1314697751
Short name T184
Test name
Test status
Simulation time 54481730 ps
CPU time 1.09 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:08 PM PST 23
Peak memory 191968 kb
Host smart-a81d6d83-406a-4459-9634-cb0e1f2d5fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314697751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1314697751
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2307767185
Short name T179
Test name
Test status
Simulation time 131055200 ps
CPU time 1.95 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:32:18 PM PST 23
Peak memory 198552 kb
Host smart-80b9b0dd-6022-4467-8a8d-fdd1548423de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307767185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2307767185
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3141095621
Short name T22
Test name
Test status
Simulation time 211467001 ps
CPU time 1.37 seconds
Started Dec 24 12:32:00 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 198492 kb
Host smart-e9cfb655-b75e-4c8a-9c34-f256301ad3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141095621 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3141095621
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3457638506
Short name T76
Test name
Test status
Simulation time 38475422 ps
CPU time 0.7 seconds
Started Dec 24 12:31:54 PM PST 23
Finished Dec 24 12:32:24 PM PST 23
Peak memory 194428 kb
Host smart-c45690d8-8624-4fc0-92a4-5dbfa7b5fe48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457638506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3457638506
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.4026872698
Short name T151
Test name
Test status
Simulation time 36627437 ps
CPU time 0.54 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:31:59 PM PST 23
Peak memory 183648 kb
Host smart-a0b4e5f3-8e39-4ce2-8b9c-5f302b7f8f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026872698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.4026872698
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.351397859
Short name T72
Test name
Test status
Simulation time 118250897 ps
CPU time 1.26 seconds
Started Dec 24 12:32:19 PM PST 23
Finished Dec 24 12:32:47 PM PST 23
Peak memory 192080 kb
Host smart-9add89d8-1cdb-4c35-b6b9-87261770132e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351397859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.351397859
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1480591501
Short name T23
Test name
Test status
Simulation time 164319924 ps
CPU time 1.68 seconds
Started Dec 24 12:31:34 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 198548 kb
Host smart-0178b06c-8906-4b0c-954d-84b1dbea9860
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480591501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1480591501
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.909441851
Short name T909
Test name
Test status
Simulation time 31686913 ps
CPU time 1.41 seconds
Started Dec 24 12:31:33 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 198340 kb
Host smart-02f814d2-9fc2-4820-a0d7-a92fa6491e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909441851 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.909441851
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3664454173
Short name T889
Test name
Test status
Simulation time 43285021 ps
CPU time 0.6 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:21 PM PST 23
Peak memory 193620 kb
Host smart-1d7df3b5-7343-405d-ad1c-e9933f9cae7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664454173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3664454173
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1427207788
Short name T166
Test name
Test status
Simulation time 151145806 ps
CPU time 0.62 seconds
Started Dec 24 12:32:06 PM PST 23
Finished Dec 24 12:32:32 PM PST 23
Peak memory 183668 kb
Host smart-9896fc6a-8362-4af2-8f1b-3b93242ff305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427207788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1427207788
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1694455093
Short name T91
Test name
Test status
Simulation time 35223533 ps
CPU time 0.79 seconds
Started Dec 24 12:32:03 PM PST 23
Finished Dec 24 12:32:30 PM PST 23
Peak memory 191812 kb
Host smart-aca1947b-20ff-49d1-99dd-4032f745fb0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694455093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1694455093
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.934753477
Short name T170
Test name
Test status
Simulation time 43425017 ps
CPU time 2.14 seconds
Started Dec 24 12:31:39 PM PST 23
Finished Dec 24 12:32:07 PM PST 23
Peak memory 198524 kb
Host smart-9a48a9db-bfad-4818-b997-f5ad0dc61f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934753477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.934753477
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2409265810
Short name T899
Test name
Test status
Simulation time 415671870 ps
CPU time 2.43 seconds
Started Dec 24 12:32:13 PM PST 23
Finished Dec 24 12:32:41 PM PST 23
Peak memory 198420 kb
Host smart-91df0108-01f1-4a94-a6d8-49caadbe1e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409265810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2409265810
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2228442948
Short name T154
Test name
Test status
Simulation time 51654195 ps
CPU time 0.84 seconds
Started Dec 24 12:31:54 PM PST 23
Finished Dec 24 12:32:26 PM PST 23
Peak memory 198208 kb
Host smart-15e15a6d-ac97-400e-9a0a-05a9b549da4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228442948 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2228442948
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.830507200
Short name T888
Test name
Test status
Simulation time 43450286 ps
CPU time 0.69 seconds
Started Dec 24 12:32:02 PM PST 23
Finished Dec 24 12:32:30 PM PST 23
Peak memory 193872 kb
Host smart-27900ede-08ae-406d-a2c5-9e4cc6edcd04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830507200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.830507200
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1570468781
Short name T169
Test name
Test status
Simulation time 29195268 ps
CPU time 0.6 seconds
Started Dec 24 12:31:23 PM PST 23
Finished Dec 24 12:31:49 PM PST 23
Peak memory 183640 kb
Host smart-3e2b48de-1621-4181-ac8f-46ea3b5f3ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570468781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1570468781
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2026890550
Short name T149
Test name
Test status
Simulation time 19634006 ps
CPU time 0.81 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:16 PM PST 23
Peak memory 191964 kb
Host smart-a559b30c-c2b7-42f5-b8cf-e2556f47ba31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026890550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2026890550
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2323260396
Short name T891
Test name
Test status
Simulation time 838976657 ps
CPU time 1.9 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:33 PM PST 23
Peak memory 198444 kb
Host smart-a7702ab3-0bba-4213-afec-83b41f5e3305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323260396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2323260396
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2604990769
Short name T906
Test name
Test status
Simulation time 463869346 ps
CPU time 1.88 seconds
Started Dec 24 12:32:07 PM PST 23
Finished Dec 24 12:32:34 PM PST 23
Peak memory 198548 kb
Host smart-5ea6900a-4ca9-42da-91a6-700d2b1033b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604990769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2604990769
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1169020855
Short name T74
Test name
Test status
Simulation time 96606536 ps
CPU time 2.33 seconds
Started Dec 24 12:31:24 PM PST 23
Finished Dec 24 12:31:52 PM PST 23
Peak memory 191956 kb
Host smart-934842a6-cb16-4f42-be15-0e14e661066e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169020855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1169020855
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1033676245
Short name T158
Test name
Test status
Simulation time 2159747254 ps
CPU time 6.45 seconds
Started Dec 24 12:31:23 PM PST 23
Finished Dec 24 12:31:55 PM PST 23
Peak memory 192072 kb
Host smart-483b54e2-0799-4c12-99d8-cffb746f4334
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033676245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1033676245
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2794266420
Short name T903
Test name
Test status
Simulation time 15227985 ps
CPU time 0.64 seconds
Started Dec 24 12:31:27 PM PST 23
Finished Dec 24 12:31:53 PM PST 23
Peak memory 193796 kb
Host smart-0ff3a672-d973-4086-9a75-bb0672a2e22b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794266420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2794266420
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3571513266
Short name T24
Test name
Test status
Simulation time 240030310 ps
CPU time 1.58 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:37 PM PST 23
Peak memory 198008 kb
Host smart-67f43eeb-9702-409d-8383-cb9ab24d468f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571513266 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3571513266
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.41338860
Short name T181
Test name
Test status
Simulation time 64690404 ps
CPU time 0.71 seconds
Started Dec 24 12:31:11 PM PST 23
Finished Dec 24 12:31:32 PM PST 23
Peak memory 194572 kb
Host smart-6a3562e0-2c7f-4d71-b6b4-f3da2cb4432f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41338860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.41338860
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2246556089
Short name T902
Test name
Test status
Simulation time 44851380 ps
CPU time 0.56 seconds
Started Dec 24 12:31:19 PM PST 23
Finished Dec 24 12:31:44 PM PST 23
Peak memory 183648 kb
Host smart-6851ebdd-27db-488d-ae99-1e7500ceabb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246556089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2246556089
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2744794322
Short name T861
Test name
Test status
Simulation time 87365912 ps
CPU time 1.35 seconds
Started Dec 24 12:34:06 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196260 kb
Host smart-179ab9ad-c70f-4e51-9fe6-d8e84946be91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744794322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2744794322
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3612881152
Short name T26
Test name
Test status
Simulation time 105504390 ps
CPU time 2.92 seconds
Started Dec 24 12:31:24 PM PST 23
Finished Dec 24 12:31:52 PM PST 23
Peak memory 198520 kb
Host smart-4e6e2248-6376-45fe-a963-e27d78be7ac7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612881152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3612881152
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2870560670
Short name T66
Test name
Test status
Simulation time 322805334 ps
CPU time 1.25 seconds
Started Dec 24 12:31:13 PM PST 23
Finished Dec 24 12:31:37 PM PST 23
Peak memory 197968 kb
Host smart-5456fa02-5c12-4c22-9714-c31820d40d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870560670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2870560670
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1314836731
Short name T164
Test name
Test status
Simulation time 12859061 ps
CPU time 0.57 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:03 PM PST 23
Peak memory 183552 kb
Host smart-adee7423-0587-4122-ae17-3a81ce218090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314836731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1314836731
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2553500127
Short name T871
Test name
Test status
Simulation time 14233748 ps
CPU time 0.56 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:15 PM PST 23
Peak memory 183544 kb
Host smart-c51071d4-5950-4fba-bcaa-703521943199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553500127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2553500127
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1209217657
Short name T162
Test name
Test status
Simulation time 19167012 ps
CPU time 0.59 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:32 PM PST 23
Peak memory 183652 kb
Host smart-8c141398-89ef-4a0b-b897-df3bd1365490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209217657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1209217657
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3095370730
Short name T873
Test name
Test status
Simulation time 17606152 ps
CPU time 0.56 seconds
Started Dec 24 12:31:51 PM PST 23
Finished Dec 24 12:32:21 PM PST 23
Peak memory 183572 kb
Host smart-886c35b2-a9ec-4eb4-96e6-7cd435d75d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095370730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3095370730
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3476412623
Short name T60
Test name
Test status
Simulation time 63620496 ps
CPU time 0.61 seconds
Started Dec 24 12:32:09 PM PST 23
Finished Dec 24 12:32:36 PM PST 23
Peak memory 183928 kb
Host smart-d18bbff6-b8d6-4984-a59c-d083ee5ade30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476412623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3476412623
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2164579476
Short name T875
Test name
Test status
Simulation time 16525752 ps
CPU time 0.64 seconds
Started Dec 24 12:31:45 PM PST 23
Finished Dec 24 12:32:14 PM PST 23
Peak memory 183544 kb
Host smart-28821e2c-9a38-4e37-9759-087ed6e1f8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164579476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2164579476
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.4163039172
Short name T190
Test name
Test status
Simulation time 47765185 ps
CPU time 0.58 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 183628 kb
Host smart-225b0e99-6cf1-4398-a926-a14377dba167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163039172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.4163039172
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1306887093
Short name T180
Test name
Test status
Simulation time 23310646 ps
CPU time 0.58 seconds
Started Dec 24 12:31:39 PM PST 23
Finished Dec 24 12:32:06 PM PST 23
Peak memory 183628 kb
Host smart-060bfaa1-4da0-440b-aab7-808819669f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306887093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1306887093
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2409210715
Short name T185
Test name
Test status
Simulation time 52426159 ps
CPU time 0.53 seconds
Started Dec 24 12:31:39 PM PST 23
Finished Dec 24 12:32:06 PM PST 23
Peak memory 183576 kb
Host smart-e1db7bcf-777b-4f49-9e27-6fe442b28b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409210715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2409210715
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1919217737
Short name T73
Test name
Test status
Simulation time 85433662 ps
CPU time 1.07 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 191728 kb
Host smart-e502b444-a92b-4233-bc8d-25ce0c8573a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919217737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1919217737
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3618215146
Short name T86
Test name
Test status
Simulation time 595657376 ps
CPU time 6.27 seconds
Started Dec 24 12:31:29 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 192080 kb
Host smart-4b824758-641f-4c6f-bf68-6f00acc4bd18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618215146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3618215146
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4052067850
Short name T77
Test name
Test status
Simulation time 17191151 ps
CPU time 0.71 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:03 PM PST 23
Peak memory 194280 kb
Host smart-60d90395-fb1e-4da7-9d56-628f1b3bc3e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052067850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4052067850
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.1830207356
Short name T892
Test name
Test status
Simulation time 24387241 ps
CPU time 0.68 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 194244 kb
Host smart-c6a34742-1cde-4a0e-9682-50afd21398cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830207356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.1830207356
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3018112319
Short name T148
Test name
Test status
Simulation time 28264351 ps
CPU time 0.54 seconds
Started Dec 24 12:34:03 PM PST 23
Finished Dec 24 12:34:41 PM PST 23
Peak memory 183252 kb
Host smart-b333329d-2bb6-4034-9011-ded37cf69678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018112319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3018112319
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2342797590
Short name T69
Test name
Test status
Simulation time 18061040 ps
CPU time 0.77 seconds
Started Dec 24 12:33:43 PM PST 23
Finished Dec 24 12:34:19 PM PST 23
Peak memory 194712 kb
Host smart-9aae25ea-48e8-4832-a64a-4bd0f9cb06c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342797590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2342797590
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.3784901500
Short name T186
Test name
Test status
Simulation time 114499062 ps
CPU time 1.65 seconds
Started Dec 24 12:31:09 PM PST 23
Finished Dec 24 12:31:32 PM PST 23
Peak memory 198540 kb
Host smart-ad35ae9f-6ebb-4af5-b3be-e9efe44b72e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784901500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.3784901500
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1883100526
Short name T863
Test name
Test status
Simulation time 31999288 ps
CPU time 0.55 seconds
Started Dec 24 12:31:58 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 183680 kb
Host smart-249cd012-1200-4d9a-8564-34f5af65ec15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883100526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1883100526
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1510269785
Short name T96
Test name
Test status
Simulation time 52991249 ps
CPU time 0.56 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:03 PM PST 23
Peak memory 183524 kb
Host smart-f61801f1-361b-4f9e-9acc-0c5339a68d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510269785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1510269785
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1224062249
Short name T13
Test name
Test status
Simulation time 28053123 ps
CPU time 0.58 seconds
Started Dec 24 12:31:32 PM PST 23
Finished Dec 24 12:31:57 PM PST 23
Peak memory 183644 kb
Host smart-3f2fac38-b60a-41b2-8b41-fedd43fdc22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224062249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1224062249
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1216482310
Short name T165
Test name
Test status
Simulation time 56982977 ps
CPU time 0.59 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 183656 kb
Host smart-c14b839d-1454-4f12-ac0d-884e557e11ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216482310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1216482310
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3646419632
Short name T62
Test name
Test status
Simulation time 21274387 ps
CPU time 0.61 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:08 PM PST 23
Peak memory 183600 kb
Host smart-3dc3fb74-7ba0-4c01-8451-331caa748215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646419632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3646419632
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.822109419
Short name T68
Test name
Test status
Simulation time 21349756 ps
CPU time 0.54 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:14 PM PST 23
Peak memory 183496 kb
Host smart-72447adb-eb60-4bd4-a34a-a26884418805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822109419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.822109419
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3943799364
Short name T94
Test name
Test status
Simulation time 61932780 ps
CPU time 0.52 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:32:12 PM PST 23
Peak memory 183520 kb
Host smart-6413d380-3a73-4133-a45c-3e89295587dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943799364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3943799364
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2336399920
Short name T869
Test name
Test status
Simulation time 18255154 ps
CPU time 0.59 seconds
Started Dec 24 12:31:38 PM PST 23
Finished Dec 24 12:32:05 PM PST 23
Peak memory 183636 kb
Host smart-878b3fad-9146-43ae-98f0-f581ebaa5d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336399920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2336399920
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4006063122
Short name T147
Test name
Test status
Simulation time 11786259 ps
CPU time 0.56 seconds
Started Dec 24 12:32:02 PM PST 23
Finished Dec 24 12:32:29 PM PST 23
Peak memory 183572 kb
Host smart-12ad9353-3070-4d8a-8e56-c1151e0627ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006063122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4006063122
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2754703220
Short name T894
Test name
Test status
Simulation time 36756677 ps
CPU time 0.55 seconds
Started Dec 24 12:31:50 PM PST 23
Finished Dec 24 12:32:20 PM PST 23
Peak memory 183660 kb
Host smart-a14ca029-0df0-4d1d-9b5d-5be5edcc7c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754703220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2754703220
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.861670730
Short name T84
Test name
Test status
Simulation time 192000580 ps
CPU time 2.57 seconds
Started Dec 24 12:33:38 PM PST 23
Finished Dec 24 12:34:17 PM PST 23
Peak memory 191660 kb
Host smart-f389560d-8d30-4ca3-bdd4-b146da7d949f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861670730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.861670730
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3160564059
Short name T178
Test name
Test status
Simulation time 666780533 ps
CPU time 2.84 seconds
Started Dec 24 12:34:09 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 191652 kb
Host smart-4f4673e6-b507-4243-a5c5-3a76e0d66229
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160564059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3160564059
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3867379535
Short name T79
Test name
Test status
Simulation time 21572716 ps
CPU time 0.66 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:36 PM PST 23
Peak memory 193676 kb
Host smart-66c97409-5d07-425a-8905-926301e1d553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867379535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3867379535
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.522931147
Short name T67
Test name
Test status
Simulation time 36117126 ps
CPU time 1.59 seconds
Started Dec 24 12:31:31 PM PST 23
Finished Dec 24 12:31:57 PM PST 23
Peak memory 198408 kb
Host smart-07813c6d-66f1-43c6-801c-5282940f6765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522931147 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.522931147
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1205106222
Short name T87
Test name
Test status
Simulation time 21840894 ps
CPU time 0.7 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:32:13 PM PST 23
Peak memory 194252 kb
Host smart-cef85d37-0804-4c83-b1e1-c0f824167725
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205106222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1205106222
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.180946213
Short name T890
Test name
Test status
Simulation time 39262521 ps
CPU time 0.55 seconds
Started Dec 24 12:31:22 PM PST 23
Finished Dec 24 12:31:48 PM PST 23
Peak memory 183564 kb
Host smart-624920f5-1dd5-4ad7-a14a-90dca7525a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180946213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.180946213
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3312870389
Short name T868
Test name
Test status
Simulation time 34119203 ps
CPU time 0.75 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 194748 kb
Host smart-f43c529a-3fd8-417e-8b75-c8373b62f572
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312870389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3312870389
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1213365826
Short name T58
Test name
Test status
Simulation time 193975219 ps
CPU time 3.35 seconds
Started Dec 24 12:31:24 PM PST 23
Finished Dec 24 12:31:52 PM PST 23
Peak memory 198416 kb
Host smart-90f1d01e-7a8e-42c4-aa55-a83825165456
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213365826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1213365826
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.465194139
Short name T102
Test name
Test status
Simulation time 127882560 ps
CPU time 1.7 seconds
Started Dec 24 12:34:04 PM PST 23
Finished Dec 24 12:34:43 PM PST 23
Peak memory 197804 kb
Host smart-1148fe57-7e2e-416a-b839-19f478fb529a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465194139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.465194139
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4229719574
Short name T881
Test name
Test status
Simulation time 40124295 ps
CPU time 0.56 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:31 PM PST 23
Peak memory 183676 kb
Host smart-ee671805-e068-4aa1-b6b3-52852483889e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229719574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4229719574
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2869344753
Short name T898
Test name
Test status
Simulation time 36352857 ps
CPU time 0.54 seconds
Started Dec 24 12:32:06 PM PST 23
Finished Dec 24 12:32:33 PM PST 23
Peak memory 183564 kb
Host smart-95df4509-173e-465f-b922-cbc767da78e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869344753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2869344753
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.951538536
Short name T150
Test name
Test status
Simulation time 14965173 ps
CPU time 0.56 seconds
Started Dec 24 12:32:11 PM PST 23
Finished Dec 24 12:32:37 PM PST 23
Peak memory 183604 kb
Host smart-4c46e432-6023-4a80-bc44-698d5e0ee661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951538536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.951538536
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1429282591
Short name T879
Test name
Test status
Simulation time 52409922 ps
CPU time 0.57 seconds
Started Dec 24 12:31:37 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 183660 kb
Host smart-7131fb46-2c4c-4192-87a1-c102fb629e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429282591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1429282591
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3792662782
Short name T155
Test name
Test status
Simulation time 23096745 ps
CPU time 0.58 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:15 PM PST 23
Peak memory 183632 kb
Host smart-001b7e0d-e555-408d-8154-3a714de59450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792662782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3792662782
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1819170736
Short name T12
Test name
Test status
Simulation time 63903898 ps
CPU time 0.57 seconds
Started Dec 24 12:32:05 PM PST 23
Finished Dec 24 12:32:31 PM PST 23
Peak memory 183660 kb
Host smart-f8927928-16c5-4bb3-9f1b-2a9fe9194dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819170736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1819170736
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.61748903
Short name T172
Test name
Test status
Simulation time 62245606 ps
CPU time 0.55 seconds
Started Dec 24 12:31:57 PM PST 23
Finished Dec 24 12:32:25 PM PST 23
Peak memory 183552 kb
Host smart-98820ef7-c10d-429b-9b9e-4b40cceeb8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61748903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.61748903
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2866123656
Short name T862
Test name
Test status
Simulation time 41422501 ps
CPU time 0.56 seconds
Started Dec 24 12:31:39 PM PST 23
Finished Dec 24 12:32:07 PM PST 23
Peak memory 183720 kb
Host smart-baa411af-cb26-4141-9d78-35c59f9810d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866123656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2866123656
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2109805207
Short name T63
Test name
Test status
Simulation time 46152697 ps
CPU time 0.57 seconds
Started Dec 24 12:31:42 PM PST 23
Finished Dec 24 12:32:09 PM PST 23
Peak memory 183640 kb
Host smart-263bebd4-4325-4547-99ec-ff98f46e5bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109805207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2109805207
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1887184997
Short name T182
Test name
Test status
Simulation time 51258118546 ps
CPU time 429.39 seconds
Started Dec 24 12:31:32 PM PST 23
Finished Dec 24 12:39:07 PM PST 23
Peak memory 200696 kb
Host smart-99e6b6a9-ae23-4648-92af-18f6bdd90c6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887184997 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1887184997
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1290122267
Short name T71
Test name
Test status
Simulation time 100789519 ps
CPU time 0.69 seconds
Started Dec 24 12:31:22 PM PST 23
Finished Dec 24 12:31:48 PM PST 23
Peak memory 194636 kb
Host smart-b0284b51-3186-4978-9f8b-68b2c5e4e5d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290122267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1290122267
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1355519507
Short name T97
Test name
Test status
Simulation time 11912925 ps
CPU time 0.61 seconds
Started Dec 24 12:31:26 PM PST 23
Finished Dec 24 12:31:53 PM PST 23
Peak memory 183568 kb
Host smart-c64782c5-dd04-476b-b420-5104369d1119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355519507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1355519507
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1555522614
Short name T897
Test name
Test status
Simulation time 44795235 ps
CPU time 1.1 seconds
Started Dec 24 12:31:28 PM PST 23
Finished Dec 24 12:31:54 PM PST 23
Peak memory 192016 kb
Host smart-d9657847-4e35-44f5-b05e-5a8f23f08136
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555522614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1555522614
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1787525943
Short name T194
Test name
Test status
Simulation time 213275345 ps
CPU time 2.04 seconds
Started Dec 24 12:31:41 PM PST 23
Finished Dec 24 12:32:10 PM PST 23
Peak memory 198364 kb
Host smart-df2b7222-db1d-4374-b83d-f18781aace2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787525943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1787525943
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3837815793
Short name T104
Test name
Test status
Simulation time 401003688 ps
CPU time 1.24 seconds
Started Dec 24 12:31:17 PM PST 23
Finished Dec 24 12:31:41 PM PST 23
Peak memory 197704 kb
Host smart-d2fd5554-aa44-4c0e-b197-67591c330903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837815793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3837815793
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3975980523
Short name T21
Test name
Test status
Simulation time 215887568 ps
CPU time 0.94 seconds
Started Dec 24 12:33:37 PM PST 23
Finished Dec 24 12:34:13 PM PST 23
Peak memory 197900 kb
Host smart-e8000b64-e302-4152-9835-bb10b0aaa00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975980523 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3975980523
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3623512381
Short name T877
Test name
Test status
Simulation time 24079094 ps
CPU time 0.6 seconds
Started Dec 24 12:31:47 PM PST 23
Finished Dec 24 12:32:16 PM PST 23
Peak memory 193872 kb
Host smart-275fd0f5-26ab-48c4-8f89-3a94fd4ec387
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623512381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3623512381
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2104549762
Short name T95
Test name
Test status
Simulation time 13480089 ps
CPU time 0.56 seconds
Started Dec 24 12:31:46 PM PST 23
Finished Dec 24 12:32:15 PM PST 23
Peak memory 183600 kb
Host smart-13aa8390-dc37-4840-8182-2357cc9f4fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104549762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2104549762
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.485764137
Short name T152
Test name
Test status
Simulation time 49146001 ps
CPU time 1.28 seconds
Started Dec 24 12:31:49 PM PST 23
Finished Dec 24 12:32:20 PM PST 23
Peak memory 192048 kb
Host smart-e513cad5-ee12-4a89-af2f-433d0d08cf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485764137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.485764137
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1917631615
Short name T882
Test name
Test status
Simulation time 462998332 ps
CPU time 1.89 seconds
Started Dec 24 12:31:24 PM PST 23
Finished Dec 24 12:31:51 PM PST 23
Peak memory 198108 kb
Host smart-f20779d6-09cc-41c4-831c-8426dce948db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917631615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1917631615
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.50807160
Short name T904
Test name
Test status
Simulation time 57376026 ps
CPU time 1.44 seconds
Started Dec 24 12:31:23 PM PST 23
Finished Dec 24 12:31:52 PM PST 23
Peak memory 198488 kb
Host smart-723e85f9-6d6f-48e2-858a-7dc0b6bcb83b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50807160 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.50807160
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2413029492
Short name T80
Test name
Test status
Simulation time 81027221 ps
CPU time 0.69 seconds
Started Dec 24 12:31:44 PM PST 23
Finished Dec 24 12:32:13 PM PST 23
Peak memory 194032 kb
Host smart-19b1ef26-e7ba-4c5a-b8db-7b4f95d9df1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413029492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2413029492
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3559304632
Short name T168
Test name
Test status
Simulation time 92968183 ps
CPU time 0.54 seconds
Started Dec 24 12:31:42 PM PST 23
Finished Dec 24 12:32:10 PM PST 23
Peak memory 183680 kb
Host smart-7e9f34a0-7b0e-4d1e-9a9a-c57872bd3f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559304632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3559304632
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1728025131
Short name T885
Test name
Test status
Simulation time 152195628 ps
CPU time 1.44 seconds
Started Dec 24 12:31:29 PM PST 23
Finished Dec 24 12:31:55 PM PST 23
Peak memory 192084 kb
Host smart-5a0b9f46-d06c-4912-aee2-0eb27b1c5a0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728025131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1728025131
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1691657300
Short name T17
Test name
Test status
Simulation time 121185481 ps
CPU time 2.26 seconds
Started Dec 24 12:31:33 PM PST 23
Finished Dec 24 12:32:00 PM PST 23
Peak memory 198472 kb
Host smart-81b78ef9-68db-4b75-aab1-37c280f4b89e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691657300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1691657300
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2353414922
Short name T173
Test name
Test status
Simulation time 214594588 ps
CPU time 1.25 seconds
Started Dec 24 12:31:38 PM PST 23
Finished Dec 24 12:32:06 PM PST 23
Peak memory 197896 kb
Host smart-4e4055fb-cb71-4abd-a4ba-2ef11bde6b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353414922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2353414922
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1663179726
Short name T167
Test name
Test status
Simulation time 3233361826 ps
CPU time 34.9 seconds
Started Dec 24 12:31:56 PM PST 23
Finished Dec 24 12:32:59 PM PST 23
Peak memory 198584 kb
Host smart-c883c8ba-8126-4bd6-a27a-690cf656f02a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663179726 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.1663179726
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.310546910
Short name T93
Test name
Test status
Simulation time 18786747 ps
CPU time 0.63 seconds
Started Dec 24 12:33:13 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 193084 kb
Host smart-8ad55153-7914-4111-8ed2-efd05b8addfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310546910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.310546910
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2230142316
Short name T171
Test name
Test status
Simulation time 35486140 ps
CPU time 0.54 seconds
Started Dec 24 12:31:19 PM PST 23
Finished Dec 24 12:31:44 PM PST 23
Peak memory 183676 kb
Host smart-a8b00b9c-0bfb-4510-8cf9-29794192fa8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230142316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2230142316
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.4285080993
Short name T19
Test name
Test status
Simulation time 110318507 ps
CPU time 0.8 seconds
Started Dec 24 12:31:32 PM PST 23
Finished Dec 24 12:31:57 PM PST 23
Peak memory 191776 kb
Host smart-f551cc85-38bc-43b2-9bac-a49b9a5e1baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285080993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.4285080993
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1320027039
Short name T883
Test name
Test status
Simulation time 80216306 ps
CPU time 1.17 seconds
Started Dec 24 12:31:39 PM PST 23
Finished Dec 24 12:32:07 PM PST 23
Peak memory 198464 kb
Host smart-8d2ba13b-27a4-41bd-afe1-83058280ce86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320027039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1320027039
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1190446120
Short name T100
Test name
Test status
Simulation time 458902816 ps
CPU time 1.84 seconds
Started Dec 24 12:31:26 PM PST 23
Finished Dec 24 12:31:54 PM PST 23
Peak memory 197956 kb
Host smart-e7a4f53a-def4-4d1e-8707-c763f1cd0fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190446120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1190446120
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3678112
Short name T187
Test name
Test status
Simulation time 18450919 ps
CPU time 1.5 seconds
Started Dec 24 12:31:40 PM PST 23
Finished Dec 24 12:32:09 PM PST 23
Peak memory 198552 kb
Host smart-f43d509b-0821-4acf-8a52-5c97b9d58f6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678112 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3678112
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1923917617
Short name T61
Test name
Test status
Simulation time 59343830 ps
CPU time 0.65 seconds
Started Dec 24 12:31:36 PM PST 23
Finished Dec 24 12:32:02 PM PST 23
Peak memory 193992 kb
Host smart-62dd8ce4-b540-40fb-8120-ede7ecbc4e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923917617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1923917617
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1675213342
Short name T174
Test name
Test status
Simulation time 12115081 ps
CPU time 0.55 seconds
Started Dec 24 12:33:34 PM PST 23
Finished Dec 24 12:34:10 PM PST 23
Peak memory 183248 kb
Host smart-6f20e775-5148-4a45-a4f2-e3e30a7d8420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675213342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1675213342
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.673012125
Short name T159
Test name
Test status
Simulation time 51349666 ps
CPU time 1.01 seconds
Started Dec 24 12:31:54 PM PST 23
Finished Dec 24 12:32:24 PM PST 23
Peak memory 192212 kb
Host smart-85124406-bc66-45ef-b86a-2e198860b83f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673012125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_
outstanding.673012125
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3316320391
Short name T183
Test name
Test status
Simulation time 28488024 ps
CPU time 1.55 seconds
Started Dec 24 12:33:45 PM PST 23
Finished Dec 24 12:34:23 PM PST 23
Peak memory 198160 kb
Host smart-77dfbbd6-3325-4bc4-ad48-362df1b7fcaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316320391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3316320391
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.787253638
Short name T893
Test name
Test status
Simulation time 65587587 ps
CPU time 1.2 seconds
Started Dec 24 12:32:00 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 197932 kb
Host smart-ce64b32e-cc08-4f4f-8f27-e70899cc0b71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787253638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.787253638
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2133172371
Short name T257
Test name
Test status
Simulation time 55904435 ps
CPU time 0.56 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 193112 kb
Host smart-dd7a1864-de19-4942-9639-cd5ee1940580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133172371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2133172371
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.4124224979
Short name T391
Test name
Test status
Simulation time 3033147468 ps
CPU time 22.69 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:55 PM PST 23
Peak memory 212308 kb
Host smart-1fdd5927-03c8-4a99-bd61-8646e4fb95c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4124224979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.4124224979
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.4059233353
Short name T648
Test name
Test status
Simulation time 1716774931 ps
CPU time 34.83 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:45:08 PM PST 23
Peak memory 198708 kb
Host smart-2dfe7c27-a148-4244-b1a2-361dccf690e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059233353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.4059233353
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3549680148
Short name T846
Test name
Test status
Simulation time 2004305014 ps
CPU time 52.76 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:45:27 PM PST 23
Peak memory 198648 kb
Host smart-d1847bf0-fb94-4eb3-bbaf-3f92738ff9c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549680148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3549680148
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2100448669
Short name T215
Test name
Test status
Simulation time 56206059826 ps
CPU time 216 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 01:48:09 PM PST 23
Peak memory 198824 kb
Host smart-16e40524-7719-445c-9fee-9e737262b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100448669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2100448669
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1975207636
Short name T113
Test name
Test status
Simulation time 1804625003 ps
CPU time 47.42 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:45:20 PM PST 23
Peak memory 198736 kb
Host smart-eb0cf809-81ed-46bf-a4a0-370af8b0c3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975207636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1975207636
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3254541168
Short name T48
Test name
Test status
Simulation time 129845024 ps
CPU time 0.73 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 215704 kb
Host smart-79b24a01-ea6e-4322-b61c-10d37dababc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254541168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3254541168
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3082132569
Short name T768
Test name
Test status
Simulation time 700248430 ps
CPU time 4.45 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 198632 kb
Host smart-f51eae9b-3edd-4c6e-970c-1c3095bad971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082132569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3082132569
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2115166949
Short name T430
Test name
Test status
Simulation time 7817136487 ps
CPU time 96.89 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:46:11 PM PST 23
Peak memory 198652 kb
Host smart-400b8ba7-e79e-4867-88ce-13b978efc762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115166949 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2115166949
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2981259151
Short name T599
Test name
Test status
Simulation time 21915416878 ps
CPU time 161.51 seconds
Started Dec 24 01:44:30 PM PST 23
Finished Dec 24 01:47:19 PM PST 23
Peak memory 214528 kb
Host smart-62bd22b2-8928-4869-a320-0f225bc179d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981259151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2981259151
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1435063603
Short name T347
Test name
Test status
Simulation time 210990238 ps
CPU time 1.08 seconds
Started Dec 24 01:44:38 PM PST 23
Finished Dec 24 01:44:40 PM PST 23
Peak memory 197160 kb
Host smart-df51f0f1-1b3f-4445-ad42-2abeeada779f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435063603 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1435063603
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.2779401139
Short name T210
Test name
Test status
Simulation time 29241737007 ps
CPU time 448.12 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:52:04 PM PST 23
Peak memory 198620 kb
Host smart-785d0c3f-5b6a-4d10-8948-049c6aaade1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779401139 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.2779401139
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2262101885
Short name T242
Test name
Test status
Simulation time 207935382 ps
CPU time 8.43 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:44:45 PM PST 23
Peak memory 198372 kb
Host smart-dcf5c32d-a0b9-4a8d-b2e4-ef34bc1639dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262101885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2262101885
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.630670897
Short name T307
Test name
Test status
Simulation time 55234043 ps
CPU time 0.53 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 193092 kb
Host smart-20789ed3-5cbe-4988-8037-a516fa3b4bc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630670897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.630670897
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2750754220
Short name T379
Test name
Test status
Simulation time 1854965962 ps
CPU time 26.12 seconds
Started Dec 24 01:44:17 PM PST 23
Finished Dec 24 01:45:01 PM PST 23
Peak memory 208180 kb
Host smart-b65810de-8722-4b8f-817c-ddd0e2b9e064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750754220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2750754220
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.964091814
Short name T537
Test name
Test status
Simulation time 2536476344 ps
CPU time 59.41 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:45:32 PM PST 23
Peak memory 198864 kb
Host smart-1b20534a-841a-4532-9f4e-6207ca5c6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964091814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.964091814
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4118562848
Short name T622
Test name
Test status
Simulation time 2412502526 ps
CPU time 124.29 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:46:36 PM PST 23
Peak memory 198672 kb
Host smart-9a2e9a2d-6705-46e5-a2fd-088314312692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118562848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4118562848
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.270284025
Short name T760
Test name
Test status
Simulation time 1337880749 ps
CPU time 63.25 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 198744 kb
Host smart-78370133-0172-4ef5-a1ee-aefc5a10dbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270284025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.270284025
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2957277926
Short name T447
Test name
Test status
Simulation time 1035122888 ps
CPU time 55.81 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:45:28 PM PST 23
Peak memory 198584 kb
Host smart-47f0f176-2d13-452e-8141-9d7de00638be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957277926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2957277926
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.384146668
Short name T291
Test name
Test status
Simulation time 221357395 ps
CPU time 2.49 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:44:39 PM PST 23
Peak memory 198164 kb
Host smart-cf345e82-4b9a-436e-9360-e53cf7181ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384146668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.384146668
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2015408555
Short name T746
Test name
Test status
Simulation time 195748653171 ps
CPU time 1639.88 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 02:11:54 PM PST 23
Peak memory 231528 kb
Host smart-72f61e00-4bcb-40ad-b399-636504cac83b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015408555 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2015408555
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3550572952
Short name T527
Test name
Test status
Simulation time 166535336959 ps
CPU time 1244.59 seconds
Started Dec 24 01:44:25 PM PST 23
Finished Dec 24 02:05:22 PM PST 23
Peak memory 242056 kb
Host smart-b50064d3-31f4-4db7-8b45-9cca2b0b97b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3550572952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3550572952
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.4214773297
Short name T663
Test name
Test status
Simulation time 140633872 ps
CPU time 0.9 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 195712 kb
Host smart-1519d0a8-d0a0-43c9-9905-4e0b586c1a3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214773297 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.4214773297
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.4292253379
Short name T789
Test name
Test status
Simulation time 86808688949 ps
CPU time 433.86 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:51:48 PM PST 23
Peak memory 198816 kb
Host smart-943502ef-77a9-44f2-855b-3c5925255925
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292253379 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.4292253379
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.2238454747
Short name T225
Test name
Test status
Simulation time 1256036797 ps
CPU time 9.03 seconds
Started Dec 24 01:44:35 PM PST 23
Finished Dec 24 01:44:47 PM PST 23
Peak memory 198732 kb
Host smart-d4d08e15-0ff6-4773-83cd-bf3b78fb3fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238454747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.2238454747
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.4233377104
Short name T400
Test name
Test status
Simulation time 29336785 ps
CPU time 0.6 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:12 PM PST 23
Peak memory 194144 kb
Host smart-d67a2f59-e4ac-4cbf-9815-d947e1960012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233377104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.4233377104
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1782715731
Short name T352
Test name
Test status
Simulation time 1077025757 ps
CPU time 19.61 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:46:27 PM PST 23
Peak memory 231380 kb
Host smart-93f68604-e270-448d-8ddd-18470bca8c31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1782715731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1782715731
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3572738973
Short name T435
Test name
Test status
Simulation time 82313417 ps
CPU time 1.16 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:46:12 PM PST 23
Peak memory 197444 kb
Host smart-4cec048a-d682-4ae6-854b-392c3f460d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572738973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3572738973
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.444018396
Short name T852
Test name
Test status
Simulation time 2055879976 ps
CPU time 27.89 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:33 PM PST 23
Peak memory 198508 kb
Host smart-70710f5a-0a36-481b-847d-434836959d5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444018396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.444018396
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3258544020
Short name T278
Test name
Test status
Simulation time 4370168009 ps
CPU time 62.38 seconds
Started Dec 24 01:46:11 PM PST 23
Finished Dec 24 01:47:15 PM PST 23
Peak memory 198800 kb
Host smart-ffbb2777-8e46-4933-91bb-b4560cf87823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258544020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3258544020
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3050534846
Short name T490
Test name
Test status
Simulation time 16044731219 ps
CPU time 67.88 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 01:47:31 PM PST 23
Peak memory 198868 kb
Host smart-06b508ee-84f4-4e1b-a373-cb61d9600e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050534846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3050534846
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1180988575
Short name T258
Test name
Test status
Simulation time 256892571 ps
CPU time 2.13 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:08 PM PST 23
Peak memory 198708 kb
Host smart-8b01ae4e-56cc-4920-9b38-ed8d69bafb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180988575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1180988575
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.4152148023
Short name T479
Test name
Test status
Simulation time 59089781012 ps
CPU time 618.01 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:55:33 PM PST 23
Peak memory 235596 kb
Host smart-9d88a558-cfc9-4736-8f4e-28faba6791ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152148023 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.4152148023
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.1566326555
Short name T385
Test name
Test status
Simulation time 29287266989 ps
CPU time 297.57 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:50:11 PM PST 23
Peak memory 232676 kb
Host smart-750d722b-1876-480c-9d95-5f468a6fe527
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566326555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.1566326555
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3024074643
Short name T283
Test name
Test status
Simulation time 48614354 ps
CPU time 1.02 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:20 PM PST 23
Peak memory 197080 kb
Host smart-53cdbcad-ab06-49e9-acf2-c8bc9df079e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024074643 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3024074643
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1901786250
Short name T664
Test name
Test status
Simulation time 42603186096 ps
CPU time 468.73 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:54:11 PM PST 23
Peak memory 198608 kb
Host smart-d9eb9d64-5880-44c8-9900-ba78d968a89d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901786250 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.1901786250
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.604373306
Short name T806
Test name
Test status
Simulation time 390695748 ps
CPU time 12.08 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:47:03 PM PST 23
Peak memory 198700 kb
Host smart-c696265e-d9a8-4727-8b7b-02e414d71eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604373306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.604373306
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.3876184433
Short name T110
Test name
Test status
Simulation time 198626172932 ps
CPU time 686.43 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:57:49 PM PST 23
Peak memory 223516 kb
Host smart-c0663518-2557-4927-a21c-3e14a03334cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876184433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.3876184433
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.hmac_stress_all_with_rand_reset.277621171
Short name T354
Test name
Test status
Simulation time 1277913224920 ps
CPU time 2477.3 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 02:27:40 PM PST 23
Peak memory 264484 kb
Host smart-60739f52-9d81-445a-92e0-85cfa3caae33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277621171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.hmac_stress_all_with_rand_reset.277621171
Directory /workspace/103.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.877718327
Short name T472
Test name
Test status
Simulation time 685065021367 ps
CPU time 2536.52 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 02:29:07 PM PST 23
Peak memory 263384 kb
Host smart-6cbc072b-2f01-4c9d-9f25-f4c8049c067b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877718327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.877718327
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.67181513
Short name T639
Test name
Test status
Simulation time 508139640057 ps
CPU time 1065.6 seconds
Started Dec 24 01:46:46 PM PST 23
Finished Dec 24 02:04:39 PM PST 23
Peak memory 242592 kb
Host smart-6f81dfc4-2b47-4a2d-a93f-dfa8d5e9d64b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67181513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.67181513
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.2410919027
Short name T305
Test name
Test status
Simulation time 105911751928 ps
CPU time 478.26 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:54:20 PM PST 23
Peak memory 229492 kb
Host smart-a59afc3a-d243-4c14-bcb7-20738816fe3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2410919027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.2410919027
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3238475
Short name T712
Test name
Test status
Simulation time 66432458645 ps
CPU time 1238.72 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 02:07:02 PM PST 23
Peak memory 247976 kb
Host smart-0a14527e-6c9b-4736-9add-bfe2f6024d09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3238475
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.3710657517
Short name T439
Test name
Test status
Simulation time 105341749866 ps
CPU time 1553.14 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:12:46 PM PST 23
Peak memory 245976 kb
Host smart-a9302ad9-2743-4b79-ae83-21468b0a64fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710657517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.3710657517
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.3513821947
Short name T798
Test name
Test status
Simulation time 82933135123 ps
CPU time 790.86 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:59:34 PM PST 23
Peak memory 215200 kb
Host smart-67e5fd65-af2c-4f71-aa5d-b9a4d6d58db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3513821947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.3513821947
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1462941354
Short name T488
Test name
Test status
Simulation time 38037810 ps
CPU time 0.56 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:19 PM PST 23
Peak memory 194140 kb
Host smart-7950be44-a24d-4553-95e0-96641e03883e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462941354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1462941354
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.632305713
Short name T438
Test name
Test status
Simulation time 386733736 ps
CPU time 9.49 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:29 PM PST 23
Peak memory 198672 kb
Host smart-bc9226b3-0fe3-406a-85e7-41c5a7ee03be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632305713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.632305713
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.727215059
Short name T771
Test name
Test status
Simulation time 1713046587 ps
CPU time 23.2 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 198744 kb
Host smart-69734895-b4f5-42a9-b57f-ce41c1f8caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727215059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.727215059
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1988128322
Short name T848
Test name
Test status
Simulation time 3288787824 ps
CPU time 33.01 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:49 PM PST 23
Peak memory 198808 kb
Host smart-8bd8e32b-1209-4009-bcb7-85a3ea5bccdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988128322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1988128322
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3745520958
Short name T481
Test name
Test status
Simulation time 6783770010 ps
CPU time 109.5 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:47:01 PM PST 23
Peak memory 198740 kb
Host smart-bf2a0db4-d682-4fc0-b616-2d3b4ee3c0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745520958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3745520958
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3962964768
Short name T540
Test name
Test status
Simulation time 516328267 ps
CPU time 24.59 seconds
Started Dec 24 01:45:01 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 198640 kb
Host smart-3b4df109-5ba8-4408-85e7-b84b785c03b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962964768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3962964768
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1879570624
Short name T217
Test name
Test status
Simulation time 23776773 ps
CPU time 0.7 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:15 PM PST 23
Peak memory 194524 kb
Host smart-3adb7b88-2615-4247-a474-df27c7f7c5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879570624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1879570624
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.9911295
Short name T541
Test name
Test status
Simulation time 28492355417 ps
CPU time 160.19 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:47:54 PM PST 23
Peak memory 214544 kb
Host smart-b49e8ee9-a0b9-41af-a215-631686b185c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9911295 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.9911295
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.205835666
Short name T468
Test name
Test status
Simulation time 56983394596 ps
CPU time 784.83 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:58:21 PM PST 23
Peak memory 209240 kb
Host smart-562a863f-5def-417d-9712-c44372d83b61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205835666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.205835666
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3535461586
Short name T494
Test name
Test status
Simulation time 99214806 ps
CPU time 0.92 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:13 PM PST 23
Peak memory 196840 kb
Host smart-46e3242b-12b6-451e-8ab9-b51a33746e46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535461586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3535461586
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3868480997
Short name T336
Test name
Test status
Simulation time 83656207874 ps
CPU time 484.21 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:53:17 PM PST 23
Peak memory 198748 kb
Host smart-f994efe0-d7cc-4c5e-b3f6-bf54e3a0ca65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868480997 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.3868480997
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.289068585
Short name T539
Test name
Test status
Simulation time 8296930603 ps
CPU time 44.56 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:46:06 PM PST 23
Peak memory 198852 kb
Host smart-baefec29-799d-4c49-b1f9-89732af2525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289068585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.289068585
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/110.hmac_stress_all_with_rand_reset.2765862975
Short name T782
Test name
Test status
Simulation time 95383994893 ps
CPU time 1126.45 seconds
Started Dec 24 01:46:47 PM PST 23
Finished Dec 24 02:05:41 PM PST 23
Peak memory 223404 kb
Host smart-082f5055-238f-449c-96fc-6095ffd27d12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765862975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.hmac_stress_all_with_rand_reset.2765862975
Directory /workspace/110.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.1095050123
Short name T630
Test name
Test status
Simulation time 67734602198 ps
CPU time 2138.89 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 02:22:03 PM PST 23
Peak memory 248004 kb
Host smart-e9a3057d-da7f-4f29-86c5-ce5b00de0169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095050123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.1095050123
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.388125761
Short name T709
Test name
Test status
Simulation time 34982801039 ps
CPU time 635.4 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:56:55 PM PST 23
Peak memory 231712 kb
Host smart-41ade188-cbe8-4694-bb87-3e6742fb15ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388125761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.388125761
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.1137766052
Short name T326
Test name
Test status
Simulation time 14631518422 ps
CPU time 786.43 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:59:27 PM PST 23
Peak memory 207136 kb
Host smart-b42e59a9-c576-41dd-a84d-560bb0ea3d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137766052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.1137766052
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.3163579291
Short name T89
Test name
Test status
Simulation time 79066417942 ps
CPU time 1198.06 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:06:51 PM PST 23
Peak memory 264360 kb
Host smart-4fb84f2f-e3e4-456f-b215-6a64167ed5c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163579291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.3163579291
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.963835878
Short name T578
Test name
Test status
Simulation time 156084450665 ps
CPU time 3627.67 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 02:47:20 PM PST 23
Peak memory 263852 kb
Host smart-78a0abf3-4859-41b4-931f-59090c3e67d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963835878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.963835878
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.1348773899
Short name T370
Test name
Test status
Simulation time 168868917291 ps
CPU time 378.51 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:52:39 PM PST 23
Peak memory 214288 kb
Host smart-9f399928-2957-485c-9797-78a85e3ca53b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348773899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.1348773899
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.444495110
Short name T117
Test name
Test status
Simulation time 415314512035 ps
CPU time 1504.55 seconds
Started Dec 24 01:46:46 PM PST 23
Finished Dec 24 02:11:59 PM PST 23
Peak memory 231132 kb
Host smart-b70d837b-e9c6-44d9-b0a1-464365fd0080
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=444495110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.444495110
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.686151500
Short name T819
Test name
Test status
Simulation time 914144240187 ps
CPU time 1170.07 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:06:23 PM PST 23
Peak memory 244024 kb
Host smart-5beb973a-bd78-41a9-a868-c30d42c9e5e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686151500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.686151500
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3253096601
Short name T631
Test name
Test status
Simulation time 21567409 ps
CPU time 0.64 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:19 PM PST 23
Peak memory 194068 kb
Host smart-3bd370ac-e1a9-40c7-bebc-a87161b286e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253096601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3253096601
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1067742292
Short name T466
Test name
Test status
Simulation time 6760029676 ps
CPU time 63.83 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:27 PM PST 23
Peak memory 230752 kb
Host smart-a37b315d-444b-4502-9674-7f769c704305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1067742292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1067742292
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.383813127
Short name T293
Test name
Test status
Simulation time 459909135 ps
CPU time 20.83 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 198732 kb
Host smart-fbfad839-938b-4756-9155-8f14f8a95f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383813127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.383813127
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1062271008
Short name T830
Test name
Test status
Simulation time 25233553121 ps
CPU time 106.87 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198640 kb
Host smart-593d04a2-d6e7-46a1-9d99-9294bd2bbde8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1062271008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1062271008
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1066256375
Short name T467
Test name
Test status
Simulation time 13402793097 ps
CPU time 42.46 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 198864 kb
Host smart-3e5d2a51-226a-4aac-aeb7-165ca2f460ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066256375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1066256375
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3908802704
Short name T300
Test name
Test status
Simulation time 27408048038 ps
CPU time 97.37 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:46:49 PM PST 23
Peak memory 198736 kb
Host smart-ce9055ec-8c73-41be-b93f-fd799ee7050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908802704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3908802704
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2186389344
Short name T805
Test name
Test status
Simulation time 515585646 ps
CPU time 1.54 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:21 PM PST 23
Peak memory 198468 kb
Host smart-14719071-320f-4de0-b506-2fa71b5f2544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186389344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2186389344
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3620568648
Short name T496
Test name
Test status
Simulation time 1399932032705 ps
CPU time 2538.74 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 02:27:33 PM PST 23
Peak memory 198844 kb
Host smart-c1de140a-8d7a-4259-90d6-e3f8fff9b34f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620568648 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3620568648
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2610791557
Short name T781
Test name
Test status
Simulation time 39788001865 ps
CPU time 194.69 seconds
Started Dec 24 01:45:07 PM PST 23
Finished Dec 24 01:48:23 PM PST 23
Peak memory 247352 kb
Host smart-18b95455-211d-4590-8017-31f2009fc59a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610791557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.2610791557
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3479262797
Short name T726
Test name
Test status
Simulation time 55412963 ps
CPU time 1.2 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:13 PM PST 23
Peak memory 196704 kb
Host smart-f5f327e2-c1ff-42e7-adbe-692e6aafe421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479262797 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3479262797
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2296935940
Short name T780
Test name
Test status
Simulation time 6939463386 ps
CPU time 344.12 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:50:57 PM PST 23
Peak memory 198832 kb
Host smart-7c9c2d66-a964-44d3-abdf-db11c7cedbf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296935940 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.2296935940
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2260826172
Short name T754
Test name
Test status
Simulation time 6758465498 ps
CPU time 71.08 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:46:25 PM PST 23
Peak memory 198876 kb
Host smart-6bbf61de-d6e1-48af-8075-7596bbf54c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260826172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2260826172
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.3455351907
Short name T246
Test name
Test status
Simulation time 44389831301 ps
CPU time 348.52 seconds
Started Dec 24 01:46:23 PM PST 23
Finished Dec 24 01:52:13 PM PST 23
Peak memory 219872 kb
Host smart-236f6bbe-956f-4192-83ac-dfb2a60a3564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455351907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.3455351907
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.1130179061
Short name T675
Test name
Test status
Simulation time 86082944697 ps
CPU time 426.24 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 247224 kb
Host smart-3c897311-3237-4de1-92ba-3e47ffb2b9e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130179061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.1130179061
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.2242876859
Short name T816
Test name
Test status
Simulation time 81239254764 ps
CPU time 306.59 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:51:59 PM PST 23
Peak memory 215220 kb
Host smart-9e018b7c-5ffa-49eb-93ec-efc35506cbdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242876859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.2242876859
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.2734678866
Short name T661
Test name
Test status
Simulation time 15560361190 ps
CPU time 775.13 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:59:47 PM PST 23
Peak memory 235992 kb
Host smart-21d428f4-5b6a-461a-8968-60341e8e8f3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734678866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.2734678866
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.3185592589
Short name T287
Test name
Test status
Simulation time 190440877574 ps
CPU time 1648.45 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 02:13:49 PM PST 23
Peak memory 237620 kb
Host smart-5d07746b-1865-4c57-b792-389edc2210c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185592589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.3185592589
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.3812007504
Short name T52
Test name
Test status
Simulation time 14943976334 ps
CPU time 239.28 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:50:52 PM PST 23
Peak memory 215428 kb
Host smart-bafb92f8-3855-42ac-99f8-3dc13f6463fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812007504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.3812007504
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2708478718
Short name T827
Test name
Test status
Simulation time 74632645703 ps
CPU time 270.66 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:51:23 PM PST 23
Peak memory 215352 kb
Host smart-2fb24596-28e6-4f1f-9fbf-21f43e4e86bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708478718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.2708478718
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.471117331
Short name T653
Test name
Test status
Simulation time 53589209014 ps
CPU time 1032.55 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 02:03:53 PM PST 23
Peak memory 242864 kb
Host smart-69328ef1-fff0-4f02-9d38-086cc0db8fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=471117331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.471117331
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.3622432851
Short name T662
Test name
Test status
Simulation time 531626853473 ps
CPU time 1203.86 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 02:06:43 PM PST 23
Peak memory 231712 kb
Host smart-5dd7f632-d79f-4aee-b330-3bc36d7c36ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622432851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.3622432851
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2268029782
Short name T686
Test name
Test status
Simulation time 62972879 ps
CPU time 0.56 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:13 PM PST 23
Peak memory 192988 kb
Host smart-ad00f8cf-baf5-4cf6-b96d-9327e84c722d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268029782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2268029782
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2144881722
Short name T560
Test name
Test status
Simulation time 2203183722 ps
CPU time 19.68 seconds
Started Dec 24 01:45:06 PM PST 23
Finished Dec 24 01:45:27 PM PST 23
Peak memory 223156 kb
Host smart-5914031e-4454-47f2-8481-5f20ad019bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144881722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2144881722
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1387076162
Short name T668
Test name
Test status
Simulation time 18954714008 ps
CPU time 43.97 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:46:02 PM PST 23
Peak memory 198852 kb
Host smart-f9f86aa0-30b2-4c68-8e84-cb6a357dda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387076162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1387076162
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.124808055
Short name T624
Test name
Test status
Simulation time 1942177484 ps
CPU time 99.2 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:47:02 PM PST 23
Peak memory 198732 kb
Host smart-62009821-1eb2-470f-8903-943e5f4a4b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124808055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.124808055
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1446701185
Short name T342
Test name
Test status
Simulation time 47551108958 ps
CPU time 129.32 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:47:34 PM PST 23
Peak memory 198824 kb
Host smart-794f517f-d280-4771-90fc-41b68dd2a473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446701185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1446701185
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1100082938
Short name T294
Test name
Test status
Simulation time 6301504198 ps
CPU time 116.29 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198856 kb
Host smart-1d656418-7704-4e47-9e34-5ae2910b8d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100082938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1100082938
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.355856509
Short name T247
Test name
Test status
Simulation time 150790777 ps
CPU time 1.44 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 198136 kb
Host smart-f25eb630-771e-40e7-ae5f-cdeb4ce29453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355856509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.355856509
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.861255495
Short name T497
Test name
Test status
Simulation time 16617587632 ps
CPU time 401.82 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:52:07 PM PST 23
Peak memory 198776 kb
Host smart-2f90a58d-3cee-4b11-a027-d2f7cd81a07d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861255495 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.861255495
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.376470044
Short name T273
Test name
Test status
Simulation time 15888019216 ps
CPU time 626.7 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:55:49 PM PST 23
Peak memory 247968 kb
Host smart-9d85a2e8-b760-4708-8030-38b73470f070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376470044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.376470044
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1381663987
Short name T552
Test name
Test status
Simulation time 215660529 ps
CPU time 1.27 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 197616 kb
Host smart-0bb9c051-df9a-49cd-bbc5-8b790ed186b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381663987 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1381663987
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3535760173
Short name T402
Test name
Test status
Simulation time 8277615727 ps
CPU time 405.32 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:52:00 PM PST 23
Peak memory 198800 kb
Host smart-57ad978e-a12a-4135-8165-23190d15d763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535760173 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.3535760173
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2136567436
Short name T783
Test name
Test status
Simulation time 518013357 ps
CPU time 17.16 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:31 PM PST 23
Peak memory 198720 kb
Host smart-fc9808d0-2215-4915-a81f-605287a9a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136567436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2136567436
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.2162289788
Short name T843
Test name
Test status
Simulation time 48504478273 ps
CPU time 1998.34 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 02:20:06 PM PST 23
Peak memory 230200 kb
Host smart-1633b663-1d77-467a-8b12-e2c3b7fe9f94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162289788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.2162289788
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.2595992250
Short name T37
Test name
Test status
Simulation time 559470983506 ps
CPU time 3068.28 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:38:01 PM PST 23
Peak memory 248248 kb
Host smart-3b37133d-2095-474a-aa48-29121e3c4b0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595992250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.2595992250
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.1432993636
Short name T742
Test name
Test status
Simulation time 106674379708 ps
CPU time 373.38 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:53:06 PM PST 23
Peak memory 231704 kb
Host smart-8369c2ae-c1e8-4ed5-a126-5bbb7c8a5d4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432993636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.1432993636
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.578578125
Short name T736
Test name
Test status
Simulation time 93129448585 ps
CPU time 658.28 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:57:51 PM PST 23
Peak memory 223552 kb
Host smart-58ff7eb7-f61d-4c6e-b3b3-f1dfcf5c3837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578578125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.578578125
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1290013586
Short name T763
Test name
Test status
Simulation time 96062588208 ps
CPU time 432.05 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:54:05 PM PST 23
Peak memory 207044 kb
Host smart-985785cd-3c64-4aca-af7e-b9fa245ae7e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290013586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.1290013586
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.411490403
Short name T565
Test name
Test status
Simulation time 99545915243 ps
CPU time 1495.68 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 02:11:42 PM PST 23
Peak memory 260556 kb
Host smart-f812ce24-f426-4885-8d1b-d34e2e278576
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411490403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.411490403
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.3194060305
Short name T503
Test name
Test status
Simulation time 107117390656 ps
CPU time 849.16 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:01:02 PM PST 23
Peak memory 212684 kb
Host smart-41e5f4fb-a550-499c-ad16-0752f1cb1d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194060305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.3194060305
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.2926397645
Short name T115
Test name
Test status
Simulation time 80185996924 ps
CPU time 3745.71 seconds
Started Dec 24 01:46:46 PM PST 23
Finished Dec 24 02:49:19 PM PST 23
Peak memory 229056 kb
Host smart-de4952d0-d309-4ea8-8513-d58603ebeb47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2926397645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.2926397645
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.3009962670
Short name T108
Test name
Test status
Simulation time 62362042854 ps
CPU time 1119.29 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 02:05:25 PM PST 23
Peak memory 231660 kb
Host smart-db23bc33-fe1e-4074-924e-8ca04f1e740a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009962670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.3009962670
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.3156013569
Short name T524
Test name
Test status
Simulation time 7606437403 ps
CPU time 145.2 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:49:17 PM PST 23
Peak memory 214688 kb
Host smart-f2cc9915-28c7-4da1-81f5-1ab9f2351235
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156013569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.3156013569
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4101088538
Short name T219
Test name
Test status
Simulation time 41184367 ps
CPU time 0.6 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:14 PM PST 23
Peak memory 193112 kb
Host smart-8a049c7f-9ac2-4f5d-933f-753801480a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101088538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4101088538
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2923260102
Short name T840
Test name
Test status
Simulation time 1470955684 ps
CPU time 24.68 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 223312 kb
Host smart-f0a2a8ae-8ac5-492f-99e9-60e36befb454
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923260102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2923260102
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.820418748
Short name T850
Test name
Test status
Simulation time 1025897284 ps
CPU time 12.96 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:31 PM PST 23
Peak memory 198648 kb
Host smart-967c1b35-09e1-405d-8772-ca65849465fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820418748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.820418748
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4157304858
Short name T574
Test name
Test status
Simulation time 1831189106 ps
CPU time 93.15 seconds
Started Dec 24 01:45:07 PM PST 23
Finished Dec 24 01:46:41 PM PST 23
Peak memory 198584 kb
Host smart-3833664d-ad49-4b57-9011-516fc8b2da15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157304858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4157304858
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.645779190
Short name T296
Test name
Test status
Simulation time 19261830704 ps
CPU time 22.88 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:34 PM PST 23
Peak memory 198812 kb
Host smart-0891b54e-98b3-48fc-85d0-61ad6c46e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645779190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.645779190
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.419724617
Short name T133
Test name
Test status
Simulation time 21552525703 ps
CPU time 79 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:46:41 PM PST 23
Peak memory 198828 kb
Host smart-6a05fffb-e69a-439d-be05-f43ef449d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419724617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.419724617
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2841311106
Short name T420
Test name
Test status
Simulation time 844065639 ps
CPU time 4.26 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 198476 kb
Host smart-8ac916e2-14d6-4d0f-885c-1a3981e05842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841311106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2841311106
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3643728049
Short name T669
Test name
Test status
Simulation time 25187456794 ps
CPU time 598.77 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:55:21 PM PST 23
Peak memory 221360 kb
Host smart-3d56d0c7-218e-4219-af69-6d6e92e9be62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643728049 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3643728049
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.135452361
Short name T405
Test name
Test status
Simulation time 44321689839 ps
CPU time 838.77 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:59:12 PM PST 23
Peak memory 226908 kb
Host smart-2c1ad055-6013-40fc-a319-50099f4b5674
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135452361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.135452361
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.4278065367
Short name T10
Test name
Test status
Simulation time 129253291 ps
CPU time 1.07 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 197856 kb
Host smart-66e3b729-a5fa-402f-bbdf-d499b17cdde5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278065367 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.4278065367
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.2773743706
Short name T383
Test name
Test status
Simulation time 185631439598 ps
CPU time 498.6 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 198868 kb
Host smart-8ef64405-b670-4775-b7c7-0e19f1770d3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773743706 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.2773743706
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2622011095
Short name T297
Test name
Test status
Simulation time 3858320380 ps
CPU time 38.67 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:57 PM PST 23
Peak memory 198816 kb
Host smart-0c13a6fa-fa1e-444a-88a2-c21b5d0d49b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622011095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2622011095
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.33834933
Short name T682
Test name
Test status
Simulation time 324582152772 ps
CPU time 1433.13 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:10:46 PM PST 23
Peak memory 245776 kb
Host smart-700cfe7f-2006-4b17-b505-1f199a30f870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33834933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.33834933
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.75067500
Short name T678
Test name
Test status
Simulation time 439501988260 ps
CPU time 1981.94 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 02:19:48 PM PST 23
Peak memory 257272 kb
Host smart-ea98c16b-2ca7-4283-bd0c-52d4c186af90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75067500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.75067500
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.61480396
Short name T779
Test name
Test status
Simulation time 466592667401 ps
CPU time 1537.9 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:12:31 PM PST 23
Peak memory 245732 kb
Host smart-e9605f0a-7a7e-45c8-899a-3fc91ef9b826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61480396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.61480396
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.3459092221
Short name T688
Test name
Test status
Simulation time 16856616542 ps
CPU time 284.14 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:51:33 PM PST 23
Peak memory 214368 kb
Host smart-f20745ab-f8bb-4659-a2d9-19b3f93c5aff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459092221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.3459092221
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.3336468790
Short name T820
Test name
Test status
Simulation time 337748036387 ps
CPU time 1506.83 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 02:11:46 PM PST 23
Peak memory 258348 kb
Host smart-aa550dc7-c482-45a5-9d05-c483909703b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336468790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.3336468790
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.2124540296
Short name T732
Test name
Test status
Simulation time 62117092585 ps
CPU time 309.04 seconds
Started Dec 24 01:46:46 PM PST 23
Finished Dec 24 01:52:02 PM PST 23
Peak memory 247044 kb
Host smart-5d6c8576-52a1-436e-8f82-b861c96ed1ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2124540296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.2124540296
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.1926839075
Short name T836
Test name
Test status
Simulation time 976710632855 ps
CPU time 1766.89 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 02:16:14 PM PST 23
Peak memory 231696 kb
Host smart-f9f96ea2-b9d0-443c-bdbd-a02b09c11ae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1926839075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.1926839075
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.3890709265
Short name T491
Test name
Test status
Simulation time 104557820820 ps
CPU time 1520.95 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 02:12:09 PM PST 23
Peak memory 250172 kb
Host smart-8507510c-af37-44af-abe1-eb59ad98b45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890709265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.3890709265
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.2060818318
Short name T4
Test name
Test status
Simulation time 20672991780 ps
CPU time 334.2 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 01:52:22 PM PST 23
Peak memory 247088 kb
Host smart-2c47036d-44dd-426c-93b9-0c57141ee761
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060818318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.2060818318
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1971198171
Short name T608
Test name
Test status
Simulation time 15795850011 ps
CPU time 150.14 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:49:23 PM PST 23
Peak memory 215480 kb
Host smart-e452b9ff-ce6f-41a4-9277-bb89343699e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971198171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1971198171
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.1185364059
Short name T857
Test name
Test status
Simulation time 79283544 ps
CPU time 0.62 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:12 PM PST 23
Peak memory 193192 kb
Host smart-e8675f4f-e8a4-4f65-bd27-61e88a151a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185364059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.1185364059
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3151611088
Short name T419
Test name
Test status
Simulation time 654510089 ps
CPU time 20.9 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:35 PM PST 23
Peak memory 214372 kb
Host smart-f8d042d9-d135-49e7-8b89-1ff1742caae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3151611088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3151611088
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1209072548
Short name T801
Test name
Test status
Simulation time 137183753 ps
CPU time 3.15 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 198692 kb
Host smart-0c86e336-03fb-451b-849d-9dec78347ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209072548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1209072548
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.981289049
Short name T116
Test name
Test status
Simulation time 2769736819 ps
CPU time 144.3 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:47:42 PM PST 23
Peak memory 198816 kb
Host smart-7d741121-1c70-4e03-a97e-3be1aac6aab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981289049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.981289049
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.682094632
Short name T757
Test name
Test status
Simulation time 38699971581 ps
CPU time 114.93 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:47:09 PM PST 23
Peak memory 198748 kb
Host smart-c429305f-5857-47a5-8ac7-1e5664295a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682094632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.682094632
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3211156885
Short name T394
Test name
Test status
Simulation time 10051883606 ps
CPU time 114.59 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:47:04 PM PST 23
Peak memory 198692 kb
Host smart-01b44755-af8f-4ef7-8af5-560ab060fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211156885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3211156885
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2700075273
Short name T723
Test name
Test status
Simulation time 220115797 ps
CPU time 3.11 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:18 PM PST 23
Peak memory 198748 kb
Host smart-836dfe5b-85c4-47c4-a7ab-f2c09db94b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700075273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2700075273
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.72269862
Short name T137
Test name
Test status
Simulation time 10927859809 ps
CPU time 461.3 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:52:51 PM PST 23
Peak memory 239780 kb
Host smart-0593d4f2-4e13-4b4d-a67e-f1b2d92b7469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72269862 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.72269862
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.1754370492
Short name T596
Test name
Test status
Simulation time 17268500864 ps
CPU time 690.2 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:56:43 PM PST 23
Peak memory 214920 kb
Host smart-9b573b1a-8b73-404d-a3db-d8aa349a8d07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754370492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.1754370492
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1655492573
Short name T790
Test name
Test status
Simulation time 104937673 ps
CPU time 0.99 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 196820 kb
Host smart-b0a2ce3a-79de-4b16-9c77-8e0f3de38105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655492573 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1655492573
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1103573717
Short name T729
Test name
Test status
Simulation time 122035804426 ps
CPU time 520.31 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:54:01 PM PST 23
Peak memory 198852 kb
Host smart-5648137d-26b2-4c66-8e7b-9a396ea73703
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103573717 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.1103573717
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1522460833
Short name T251
Test name
Test status
Simulation time 33284888700 ps
CPU time 71.54 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198920 kb
Host smart-55fa4301-b432-464b-8415-27fa436c93cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522460833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1522460833
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/150.hmac_stress_all_with_rand_reset.3573601642
Short name T401
Test name
Test status
Simulation time 36945267884 ps
CPU time 593.91 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:56:47 PM PST 23
Peak memory 239836 kb
Host smart-9f0d96db-2151-477f-8cf1-9fdd934055e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573601642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.hmac_stress_all_with_rand_reset.3573601642
Directory /workspace/150.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.hmac_stress_all_with_rand_reset.85908996
Short name T793
Test name
Test status
Simulation time 349174158843 ps
CPU time 1352.31 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:09:25 PM PST 23
Peak memory 215492 kb
Host smart-4a272aa1-c8ad-472e-972c-c51733893b97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85908996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.hmac_stress_all_with_rand_reset.85908996
Directory /workspace/152.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.374092821
Short name T136
Test name
Test status
Simulation time 204171120493 ps
CPU time 3571.33 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:46:24 PM PST 23
Peak memory 264384 kb
Host smart-b1563ef1-0749-4e47-aa7f-30b56dde8a30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374092821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.374092821
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.2305620724
Short name T459
Test name
Test status
Simulation time 229404847362 ps
CPU time 1989.01 seconds
Started Dec 24 01:47:01 PM PST 23
Finished Dec 24 02:20:12 PM PST 23
Peak memory 231620 kb
Host smart-05580f9b-3228-476b-9ef1-a96ee9f55c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305620724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.2305620724
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.548310922
Short name T35
Test name
Test status
Simulation time 10091439349 ps
CPU time 489.28 seconds
Started Dec 24 01:46:50 PM PST 23
Finished Dec 24 01:55:07 PM PST 23
Peak memory 239872 kb
Host smart-563f10f3-1634-4733-b4f8-dcb8747a514f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548310922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.548310922
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.2752451562
Short name T443
Test name
Test status
Simulation time 9933634191 ps
CPU time 194.05 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 01:50:13 PM PST 23
Peak memory 198964 kb
Host smart-80a1f4e6-0f8b-4fcf-bfff-4ed43e9ad0e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2752451562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.2752451562
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.4017438524
Short name T758
Test name
Test status
Simulation time 1442986288 ps
CPU time 31.57 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:47:24 PM PST 23
Peak memory 198788 kb
Host smart-f86cce43-3c5c-40c7-a69c-6b2bee8e2ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017438524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.4017438524
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.1929255450
Short name T269
Test name
Test status
Simulation time 21898956688 ps
CPU time 191.66 seconds
Started Dec 24 01:46:53 PM PST 23
Finished Dec 24 01:50:11 PM PST 23
Peak memory 211960 kb
Host smart-59220dff-63cc-4bbf-8dd0-edcd5f504bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929255450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.1929255450
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.1243588038
Short name T551
Test name
Test status
Simulation time 827784728653 ps
CPU time 950.56 seconds
Started Dec 24 01:47:03 PM PST 23
Finished Dec 24 02:02:54 PM PST 23
Peak memory 215236 kb
Host smart-e80855dd-ec89-498a-b56c-9bbf21b5679e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243588038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.1243588038
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2834250662
Short name T778
Test name
Test status
Simulation time 26291077 ps
CPU time 0.57 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:21 PM PST 23
Peak memory 193064 kb
Host smart-002e0994-13db-4382-b80b-2f84287ddf58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834250662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2834250662
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3796850953
Short name T465
Test name
Test status
Simulation time 469242220 ps
CPU time 20.35 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:45:29 PM PST 23
Peak memory 226396 kb
Host smart-71824c72-b081-4ce6-86e3-d29b71685062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796850953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3796850953
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1793114518
Short name T825
Test name
Test status
Simulation time 1558454204 ps
CPU time 28.47 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:45:54 PM PST 23
Peak memory 198772 kb
Host smart-573c8369-8dea-4027-a517-4e0e9371ee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793114518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1793114518
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1130771361
Short name T554
Test name
Test status
Simulation time 3741749065 ps
CPU time 46.2 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:58 PM PST 23
Peak memory 198824 kb
Host smart-47efb223-1162-4ae8-b490-28cec7a0bb56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1130771361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1130771361
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1933525173
Short name T212
Test name
Test status
Simulation time 7316959287 ps
CPU time 86.15 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:46:51 PM PST 23
Peak memory 198808 kb
Host smart-f3fc767d-9b0f-4644-802e-f3a125480897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933525173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1933525173
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2987431840
Short name T403
Test name
Test status
Simulation time 1649489574 ps
CPU time 11.29 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:30 PM PST 23
Peak memory 198720 kb
Host smart-d326e7f2-d86b-4f87-8718-243a07173990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987431840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2987431840
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.665849391
Short name T474
Test name
Test status
Simulation time 262843126 ps
CPU time 3.02 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 198556 kb
Host smart-38581349-e6af-44af-9748-d878256896fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665849391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.665849391
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1619945394
Short name T416
Test name
Test status
Simulation time 58870787610 ps
CPU time 711.44 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:57:06 PM PST 23
Peak memory 198860 kb
Host smart-093663f5-f8c5-4a76-a560-da1032b1bf5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619945394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1619945394
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.3162367312
Short name T123
Test name
Test status
Simulation time 384837671423 ps
CPU time 3430.51 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 02:42:33 PM PST 23
Peak memory 248020 kb
Host smart-8e9ba572-e3e6-4682-97d3-ec75e63d9255
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162367312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.3162367312
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1082830508
Short name T595
Test name
Test status
Simulation time 93918182 ps
CPU time 0.88 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:17 PM PST 23
Peak memory 196620 kb
Host smart-d307adf5-4473-4a6b-8cd2-c549ba15a232
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082830508 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1082830508
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3138933342
Short name T784
Test name
Test status
Simulation time 126612638058 ps
CPU time 409.26 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:52:06 PM PST 23
Peak memory 198876 kb
Host smart-bfa8e517-71de-4a73-ae2e-39e408f1d20c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138933342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.3138933342
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2582788999
Short name T222
Test name
Test status
Simulation time 5307485392 ps
CPU time 43.49 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:46:02 PM PST 23
Peak memory 197616 kb
Host smart-ddac1df3-3ff2-4c8f-8802-c7d87d670c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582788999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2582788999
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/160.hmac_stress_all_with_rand_reset.2950403737
Short name T319
Test name
Test status
Simulation time 28395525200 ps
CPU time 1248.8 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:07:41 PM PST 23
Peak memory 239744 kb
Host smart-47403aa8-f1b7-4e3b-9666-82b35fe484c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2950403737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.hmac_stress_all_with_rand_reset.2950403737
Directory /workspace/160.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.83052667
Short name T432
Test name
Test status
Simulation time 90510074410 ps
CPU time 646.32 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:57:38 PM PST 23
Peak memory 223504 kb
Host smart-5f6df0e1-3c4d-4116-85a6-98143ad28e22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83052667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.83052667
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.369223677
Short name T53
Test name
Test status
Simulation time 65816002977 ps
CPU time 558.95 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 01:56:18 PM PST 23
Peak memory 213652 kb
Host smart-ad65a6eb-41c8-40fe-84e9-f805609f70ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=369223677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.369223677
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.491584774
Short name T122
Test name
Test status
Simulation time 470706041613 ps
CPU time 1573.34 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 02:13:13 PM PST 23
Peak memory 215268 kb
Host smart-4c4eabc6-1134-46a2-90f2-1d48e43fe5b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491584774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.491584774
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1652319919
Short name T564
Test name
Test status
Simulation time 21354890826 ps
CPU time 950.32 seconds
Started Dec 24 01:46:51 PM PST 23
Finished Dec 24 02:02:49 PM PST 23
Peak memory 206920 kb
Host smart-df1dfb80-c681-4016-a51a-8fe5d9b7624e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652319919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1652319919
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.3806749230
Short name T612
Test name
Test status
Simulation time 165478133010 ps
CPU time 2714.92 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:32:14 PM PST 23
Peak memory 247736 kb
Host smart-6750e4ee-955d-45f8-9b62-fc3fb33ad5ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3806749230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.3806749230
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.1315079051
Short name T361
Test name
Test status
Simulation time 201134907375 ps
CPU time 1749.86 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:16:03 PM PST 23
Peak memory 225152 kb
Host smart-4a52b0c4-952c-46ae-a029-d39134b5d42f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315079051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.1315079051
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1116158312
Short name T512
Test name
Test status
Simulation time 653253175832 ps
CPU time 1669.93 seconds
Started Dec 24 01:47:03 PM PST 23
Finished Dec 24 02:14:54 PM PST 23
Peak memory 247996 kb
Host smart-9a5ad7af-6cbe-418a-b633-6f7801f7b866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116158312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1116158312
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.1671873086
Short name T351
Test name
Test status
Simulation time 177348987427 ps
CPU time 1735.1 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:15:48 PM PST 23
Peak memory 261020 kb
Host smart-e76ae01a-eaff-4791-a1a2-2432c3b70d16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671873086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.1671873086
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.321358641
Short name T513
Test name
Test status
Simulation time 13915537 ps
CPU time 0.55 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 193108 kb
Host smart-78548c7b-363d-442f-941d-06a8323788ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321358641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.321358641
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2733085546
Short name T817
Test name
Test status
Simulation time 498359189 ps
CPU time 16.83 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:42 PM PST 23
Peak memory 218096 kb
Host smart-84c3675e-c2de-4344-bbca-a1fbf83facaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733085546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2733085546
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1331616264
Short name T233
Test name
Test status
Simulation time 4326240341 ps
CPU time 40.25 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 198812 kb
Host smart-dc30c99a-7343-4f45-b220-87592f62dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331616264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1331616264
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1737753494
Short name T517
Test name
Test status
Simulation time 239717680 ps
CPU time 11.85 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:31 PM PST 23
Peak memory 198652 kb
Host smart-40fd7955-7c08-4bd4-a38a-a9ad735f9650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737753494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1737753494
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2854945437
Short name T802
Test name
Test status
Simulation time 8589868596 ps
CPU time 156.69 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:48:02 PM PST 23
Peak memory 198896 kb
Host smart-b9fa0c64-fde7-49de-b8eb-396d501f9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854945437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2854945437
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3595605300
Short name T543
Test name
Test status
Simulation time 27901080639 ps
CPU time 85.95 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:46:44 PM PST 23
Peak memory 198852 kb
Host smart-b162be67-7f4d-48d7-a8e8-3350b9872fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595605300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3595605300
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3565389985
Short name T579
Test name
Test status
Simulation time 206069271 ps
CPU time 1.05 seconds
Started Dec 24 01:45:06 PM PST 23
Finished Dec 24 01:45:09 PM PST 23
Peak memory 196528 kb
Host smart-2d91e42d-f379-4a1e-af8e-8cde21ae6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565389985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3565389985
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2115108828
Short name T532
Test name
Test status
Simulation time 371990227444 ps
CPU time 1139.22 seconds
Started Dec 24 01:45:06 PM PST 23
Finished Dec 24 02:04:07 PM PST 23
Peak memory 207012 kb
Host smart-77a3db3f-496e-4e01-922c-83e209be974c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115108828 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2115108828
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1640889290
Short name T6
Test name
Test status
Simulation time 96229875155 ps
CPU time 395.57 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:52:00 PM PST 23
Peak memory 215264 kb
Host smart-16878af5-d61b-4776-a330-068917fb05fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1640889290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.1640889290
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2049200993
Short name T704
Test name
Test status
Simulation time 112387511 ps
CPU time 1.14 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 197364 kb
Host smart-1cdf5e24-423b-462a-8ec5-37b7d5810a5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049200993 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2049200993
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.3823846534
Short name T643
Test name
Test status
Simulation time 18092362415 ps
CPU time 381.79 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:51:31 PM PST 23
Peak memory 198752 kb
Host smart-31f85587-60e0-4397-b08a-1a812ec8c050
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823846534 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.3823846534
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3480280342
Short name T516
Test name
Test status
Simulation time 10173714277 ps
CPU time 55.17 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:46:14 PM PST 23
Peak memory 198760 kb
Host smart-fb31b3a6-5a32-4504-90f5-6aeaa854e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480280342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3480280342
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.2468771551
Short name T412
Test name
Test status
Simulation time 38072505372 ps
CPU time 1812.89 seconds
Started Dec 24 01:46:51 PM PST 23
Finished Dec 24 02:17:11 PM PST 23
Peak memory 240788 kb
Host smart-311ba065-d9b1-438a-8bf6-53bb4453fcba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2468771551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.2468771551
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.952528861
Short name T585
Test name
Test status
Simulation time 213030228029 ps
CPU time 708.28 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:58:41 PM PST 23
Peak memory 230052 kb
Host smart-a3d94345-28ab-48a3-8e75-17a8438f2f97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952528861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.952528861
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.305764283
Short name T764
Test name
Test status
Simulation time 79408087266 ps
CPU time 2055.95 seconds
Started Dec 24 01:46:53 PM PST 23
Finished Dec 24 02:21:15 PM PST 23
Peak memory 241936 kb
Host smart-ea225f44-a2d9-4329-82d3-ab3871509219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305764283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.305764283
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.1777437701
Short name T650
Test name
Test status
Simulation time 135422504415 ps
CPU time 1804.35 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:17:03 PM PST 23
Peak memory 248080 kb
Host smart-5538ec28-27ea-4502-ade4-a36f921a86a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1777437701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.1777437701
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.2658458050
Short name T833
Test name
Test status
Simulation time 516347701910 ps
CPU time 3211.74 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:40:31 PM PST 23
Peak memory 242896 kb
Host smart-d5b6673d-f6a3-4499-825e-200f687fc942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658458050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.2658458050
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.1593812966
Short name T694
Test name
Test status
Simulation time 5137840542 ps
CPU time 267.79 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 01:51:20 PM PST 23
Peak memory 207144 kb
Host smart-22f2cbb2-a619-407b-aa0f-ce65ea9729d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593812966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.1593812966
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.3015599759
Short name T588
Test name
Test status
Simulation time 403119623742 ps
CPU time 933.55 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:02:32 PM PST 23
Peak memory 215356 kb
Host smart-3787a7ab-0c9e-43e7-a655-604d4498f075
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015599759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.3015599759
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.3397150549
Short name T377
Test name
Test status
Simulation time 108547610435 ps
CPU time 516.24 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:55:28 PM PST 23
Peak memory 231532 kb
Host smart-8fb584c8-6c07-4559-a1ad-a1d4605a14e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397150549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.3397150549
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3972350049
Short name T733
Test name
Test status
Simulation time 24807270 ps
CPU time 0.56 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 193072 kb
Host smart-60647dc6-3beb-4435-abae-d5b82577da2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972350049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3972350049
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3203537062
Short name T681
Test name
Test status
Simulation time 84061314 ps
CPU time 0.91 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:17 PM PST 23
Peak memory 196912 kb
Host smart-23df7f97-9c7a-417f-aeea-dd8a1f2964b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203537062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3203537062
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2333814181
Short name T635
Test name
Test status
Simulation time 3382046037 ps
CPU time 12.82 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 198932 kb
Host smart-2e4c8164-56f0-4208-92bc-3e6000d2e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333814181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2333814181
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.687557400
Short name T28
Test name
Test status
Simulation time 2595066572 ps
CPU time 89.59 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:46:53 PM PST 23
Peak memory 198860 kb
Host smart-b87a5290-02f9-4a55-8e4a-f6664443b79f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687557400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.687557400
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.536468463
Short name T315
Test name
Test status
Simulation time 16476271532 ps
CPU time 131.31 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:47:28 PM PST 23
Peak memory 198852 kb
Host smart-bdabcab3-47eb-48ac-9655-10e6ced859e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536468463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.536468463
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_smoke.82692495
Short name T471
Test name
Test status
Simulation time 470082333 ps
CPU time 1.03 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:13 PM PST 23
Peak memory 197456 kb
Host smart-4e4140e5-b970-4aa9-9ce4-6ef74a11d40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82692495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.82692495
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2819772228
Short name T822
Test name
Test status
Simulation time 301733996002 ps
CPU time 722.9 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:57:24 PM PST 23
Peak memory 198732 kb
Host smart-a4d7a726-f7fd-46e3-9ae4-209e6bbde670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819772228 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2819772228
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3295092030
Short name T656
Test name
Test status
Simulation time 102306797 ps
CPU time 1.07 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:14 PM PST 23
Peak memory 197676 kb
Host smart-7e35e5e5-601b-4b24-8229-f711d968e02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295092030 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3295092030
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1017189831
Short name T826
Test name
Test status
Simulation time 40932417038 ps
CPU time 466.77 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:53:04 PM PST 23
Peak memory 198884 kb
Host smart-6c14122b-158c-4312-b42f-01110d28a589
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017189831 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1017189831
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2225771779
Short name T266
Test name
Test status
Simulation time 661822877 ps
CPU time 11.85 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:45:34 PM PST 23
Peak memory 198612 kb
Host smart-4f3af609-fd50-465d-b638-f1ddd86217c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225771779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2225771779
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.254163433
Short name T34
Test name
Test status
Simulation time 175314411664 ps
CPU time 1701.66 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:15:21 PM PST 23
Peak memory 260620 kb
Host smart-43d1c3f3-9c76-4ede-8238-546dcaf44823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254163433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.254163433
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.275313976
Short name T142
Test name
Test status
Simulation time 291536753200 ps
CPU time 2496.03 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 02:28:28 PM PST 23
Peak memory 256232 kb
Host smart-739f1295-6487-4d49-ba99-45cc073703da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275313976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.275313976
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.2913684025
Short name T753
Test name
Test status
Simulation time 51636543892 ps
CPU time 2217.45 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:23:56 PM PST 23
Peak memory 241920 kb
Host smart-f53afe81-a87b-4ea4-bfa9-94c99cc0d0b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913684025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.2913684025
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.3757893492
Short name T651
Test name
Test status
Simulation time 198461156484 ps
CPU time 2329.99 seconds
Started Dec 24 01:46:51 PM PST 23
Finished Dec 24 02:25:49 PM PST 23
Peak memory 215308 kb
Host smart-1608cb2e-1539-45e0-bcae-0b5ab3f5df96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3757893492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.3757893492
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.1218043498
Short name T707
Test name
Test status
Simulation time 43191602446 ps
CPU time 674.59 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 01:58:14 PM PST 23
Peak memory 215336 kb
Host smart-6bcced9f-c8fc-4717-a3e7-b1cd182bf52a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218043498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.1218043498
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.3340249204
Short name T775
Test name
Test status
Simulation time 55937326931 ps
CPU time 224.3 seconds
Started Dec 24 01:47:06 PM PST 23
Finished Dec 24 01:50:52 PM PST 23
Peak memory 215140 kb
Host smart-6d6eb2cf-6870-46fd-afb1-98f4f88f3e7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340249204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.3340249204
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.989610081
Short name T849
Test name
Test status
Simulation time 173976568383 ps
CPU time 427.82 seconds
Started Dec 24 01:46:56 PM PST 23
Finished Dec 24 01:54:08 PM PST 23
Peak memory 248088 kb
Host smart-0992ce3f-316d-4fc7-8cfd-6373c36d72ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=989610081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.989610081
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.1813796866
Short name T231
Test name
Test status
Simulation time 37374865114 ps
CPU time 1535.98 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 02:12:35 PM PST 23
Peak memory 237580 kb
Host smart-a2a0a4fd-37a0-4d99-b91d-eac5d4d5b105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813796866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.1813796866
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.308112924
Short name T526
Test name
Test status
Simulation time 19170793204 ps
CPU time 298.33 seconds
Started Dec 24 01:46:57 PM PST 23
Finished Dec 24 01:51:59 PM PST 23
Peak memory 215272 kb
Host smart-95a45593-ceea-41d0-825e-33cb5bfe912d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=308112924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.308112924
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.937697752
Short name T82
Test name
Test status
Simulation time 182042211787 ps
CPU time 2234.89 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 02:24:14 PM PST 23
Peak memory 223916 kb
Host smart-ee789a96-938e-4a42-aa84-493d79289b74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937697752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.937697752
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3098089553
Short name T685
Test name
Test status
Simulation time 14120790 ps
CPU time 0.55 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 192828 kb
Host smart-c509b8f3-a044-4d9c-a752-50cbede1ec1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098089553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3098089553
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.162783535
Short name T407
Test name
Test status
Simulation time 2816622875 ps
CPU time 24.03 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:42 PM PST 23
Peak memory 224224 kb
Host smart-8ec3d2f6-ae15-4680-9e90-52f56bc74bf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162783535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.162783535
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.58217611
Short name T486
Test name
Test status
Simulation time 52803341 ps
CPU time 2.25 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 198720 kb
Host smart-487686be-a8b3-49b4-90f3-a804f44c53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58217611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.58217611
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1633158373
Short name T501
Test name
Test status
Simulation time 5279948045 ps
CPU time 61.61 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:46:25 PM PST 23
Peak memory 198564 kb
Host smart-9490465c-d494-4ace-932f-d727dafb6070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633158373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1633158373
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1114933567
Short name T252
Test name
Test status
Simulation time 3065008036 ps
CPU time 23.77 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:47 PM PST 23
Peak memory 198640 kb
Host smart-d1796477-4454-44ec-99ec-79731ead46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114933567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1114933567
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2316959284
Short name T515
Test name
Test status
Simulation time 6317109270 ps
CPU time 42.53 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:46:05 PM PST 23
Peak memory 198824 kb
Host smart-4bdfaa61-4d60-4200-858b-9ae10747c1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316959284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2316959284
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2244952816
Short name T299
Test name
Test status
Simulation time 145301020 ps
CPU time 1.82 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 198652 kb
Host smart-4bffbd5f-94e3-400e-be0e-8a7ec19e39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244952816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2244952816
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1680634497
Short name T406
Test name
Test status
Simulation time 29864297819 ps
CPU time 254.93 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:49:55 PM PST 23
Peak memory 198880 kb
Host smart-c289caab-3455-4937-9ff3-f10c7c28f462
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680634497 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1680634497
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.1499584823
Short name T530
Test name
Test status
Simulation time 604901480747 ps
CPU time 2113.41 seconds
Started Dec 24 01:45:51 PM PST 23
Finished Dec 24 02:21:06 PM PST 23
Peak memory 229132 kb
Host smart-cbd6a1c3-6270-4999-aadd-419143df33da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499584823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.1499584823
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.952402772
Short name T566
Test name
Test status
Simulation time 55904152 ps
CPU time 0.99 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:45:40 PM PST 23
Peak memory 196052 kb
Host smart-6d0443fc-6122-4cc3-aed8-8c58d086d6a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952402772 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.952402772
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.3437205676
Short name T248
Test name
Test status
Simulation time 46151329125 ps
CPU time 452.42 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 01:53:10 PM PST 23
Peak memory 198864 kb
Host smart-6c3fbbb1-cb3d-4373-adb8-2c24bdb03676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437205676 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.3437205676
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1891471818
Short name T462
Test name
Test status
Simulation time 5581597916 ps
CPU time 79.87 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:42 PM PST 23
Peak memory 198748 kb
Host smart-ebb5868c-97af-483c-bb9b-76bcc74fddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891471818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1891471818
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.1401243283
Short name T582
Test name
Test status
Simulation time 33113339698 ps
CPU time 1204.18 seconds
Started Dec 24 01:47:03 PM PST 23
Finished Dec 24 02:07:08 PM PST 23
Peak memory 240272 kb
Host smart-f7c84b8d-4b62-420f-bd4b-06adb282abd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401243283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.1401243283
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.619227047
Short name T457
Test name
Test status
Simulation time 110718829553 ps
CPU time 1469.96 seconds
Started Dec 24 01:47:02 PM PST 23
Finished Dec 24 02:11:33 PM PST 23
Peak memory 244984 kb
Host smart-13c9a6af-5b7b-445b-87bb-52da8ea63726
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619227047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.619227047
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.769747230
Short name T460
Test name
Test status
Simulation time 12076898090 ps
CPU time 187.2 seconds
Started Dec 24 01:46:55 PM PST 23
Finished Dec 24 01:50:07 PM PST 23
Peak memory 227684 kb
Host smart-292c302e-147c-4d45-9292-fa43afe65463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769747230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.769747230
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3716555973
Short name T404
Test name
Test status
Simulation time 10301190218 ps
CPU time 522.06 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 01:55:41 PM PST 23
Peak memory 208776 kb
Host smart-a363dc2d-1e52-47d3-95b9-68f05f14c536
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716555973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3716555973
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.4193646960
Short name T690
Test name
Test status
Simulation time 119545338741 ps
CPU time 5130.18 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 03:12:30 PM PST 23
Peak memory 257304 kb
Host smart-954e9ef8-08eb-4153-a63e-5f2b3e4652bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193646960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.4193646960
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.1325934402
Short name T389
Test name
Test status
Simulation time 456253324754 ps
CPU time 3308.98 seconds
Started Dec 24 01:47:02 PM PST 23
Finished Dec 24 02:42:13 PM PST 23
Peak memory 275672 kb
Host smart-469b0dd2-a9f1-4ba6-b4e6-994d5dd583d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325934402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.1325934402
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.2477452459
Short name T64
Test name
Test status
Simulation time 99572559817 ps
CPU time 377.95 seconds
Started Dec 24 01:47:06 PM PST 23
Finished Dec 24 01:53:26 PM PST 23
Peak memory 247352 kb
Host smart-15360aab-0f3f-49ce-8f36-689d0806be27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477452459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.2477452459
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.3204287229
Short name T413
Test name
Test status
Simulation time 77270630736 ps
CPU time 3385.16 seconds
Started Dec 24 01:46:57 PM PST 23
Finished Dec 24 02:43:26 PM PST 23
Peak memory 231704 kb
Host smart-84806764-097d-4e1d-a36b-6f7bdf6af6d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204287229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.3204287229
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.2099191548
Short name T111
Test name
Test status
Simulation time 35549004891 ps
CPU time 1725.39 seconds
Started Dec 24 01:46:55 PM PST 23
Finished Dec 24 02:15:45 PM PST 23
Peak memory 243984 kb
Host smart-701dc80a-cbd7-43e6-b625-2231b5c049e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099191548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.2099191548
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.3752374420
Short name T666
Test name
Test status
Simulation time 81951624284 ps
CPU time 322.02 seconds
Started Dec 24 01:46:54 PM PST 23
Finished Dec 24 01:52:21 PM PST 23
Peak memory 214660 kb
Host smart-cfea3a6d-675c-4a60-bbf3-2d98ee6dc127
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752374420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.3752374420
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2206366104
Short name T366
Test name
Test status
Simulation time 26237572 ps
CPU time 0.59 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:31 PM PST 23
Peak memory 193124 kb
Host smart-9025e688-e7fc-4b6b-b055-e1858634d03a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206366104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2206366104
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.653940753
Short name T452
Test name
Test status
Simulation time 1026687740 ps
CPU time 30.63 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:44:59 PM PST 23
Peak memory 198716 kb
Host smart-672bc13e-833a-4bd9-bf8f-b9efcb85f501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653940753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.653940753
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3984541794
Short name T434
Test name
Test status
Simulation time 369031447 ps
CPU time 15.7 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:46:09 PM PST 23
Peak memory 198172 kb
Host smart-13660775-4335-4692-b95a-f2a7bc55b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984541794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3984541794
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1671552481
Short name T373
Test name
Test status
Simulation time 7075544364 ps
CPU time 92.91 seconds
Started Dec 24 01:44:19 PM PST 23
Finished Dec 24 01:46:09 PM PST 23
Peak memory 198744 kb
Host smart-7a91f7fc-e40e-4ff5-98a0-d788d00a5483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671552481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1671552481
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1502592038
Short name T797
Test name
Test status
Simulation time 882932182 ps
CPU time 42.24 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 198684 kb
Host smart-c9fca4da-571b-4527-aa96-8d427470ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502592038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1502592038
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.681412486
Short name T719
Test name
Test status
Simulation time 5594612812 ps
CPU time 69.87 seconds
Started Dec 24 01:44:16 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 198864 kb
Host smart-fc5156bb-84b5-4ee1-8f2d-8643191eac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681412486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.681412486
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2887226625
Short name T45
Test name
Test status
Simulation time 143356913 ps
CPU time 1.03 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 217112 kb
Host smart-5307bc76-1586-4220-a168-0d22bf100f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887226625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2887226625
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.437965049
Short name T356
Test name
Test status
Simulation time 1409893314 ps
CPU time 3.75 seconds
Started Dec 24 01:44:11 PM PST 23
Finished Dec 24 01:44:35 PM PST 23
Peak memory 198668 kb
Host smart-a525d4c8-ca5d-4b9e-ab48-7ff2061a0908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437965049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.437965049
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4250191932
Short name T386
Test name
Test status
Simulation time 280453327427 ps
CPU time 599.96 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:55:53 PM PST 23
Peak memory 239248 kb
Host smart-da713db8-61a1-4359-8fd5-6ce187e4f082
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250191932 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4250191932
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2007146822
Short name T589
Test name
Test status
Simulation time 68522792 ps
CPU time 0.91 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:45:54 PM PST 23
Peak memory 195372 kb
Host smart-ac6d25c8-d419-49e7-b741-68dcecbb65d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007146822 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2007146822
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.3639952329
Short name T265
Test name
Test status
Simulation time 29249264367 ps
CPU time 478.51 seconds
Started Dec 24 01:44:40 PM PST 23
Finished Dec 24 01:52:39 PM PST 23
Peak memory 198832 kb
Host smart-801af3b4-0431-47f3-82a6-5e0e08ab651b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639952329 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.3639952329
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.318471709
Short name T591
Test name
Test status
Simulation time 2576435389 ps
CPU time 31.04 seconds
Started Dec 24 01:45:50 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 198164 kb
Host smart-555dd920-372b-40cc-82c1-e10117cef2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318471709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.318471709
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2281128816
Short name T696
Test name
Test status
Simulation time 12449694 ps
CPU time 0.58 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:46:08 PM PST 23
Peak memory 193044 kb
Host smart-f24137e3-7fc7-4050-a379-340da36a50fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281128816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2281128816
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3890841962
Short name T521
Test name
Test status
Simulation time 2627012216 ps
CPU time 40.2 seconds
Started Dec 24 01:45:48 PM PST 23
Finished Dec 24 01:46:29 PM PST 23
Peak memory 207016 kb
Host smart-590792be-40ab-4851-9971-57b9b95b3d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890841962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3890841962
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2648371738
Short name T776
Test name
Test status
Simulation time 1918093093 ps
CPU time 44.05 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:47:31 PM PST 23
Peak memory 198744 kb
Host smart-3fd93c90-ec89-4e37-926f-d108b1aa0c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648371738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2648371738
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2639541295
Short name T301
Test name
Test status
Simulation time 1774311573 ps
CPU time 88.21 seconds
Started Dec 24 01:45:41 PM PST 23
Finished Dec 24 01:47:10 PM PST 23
Peak memory 198700 kb
Host smart-25e6daa6-6fab-4595-8ac0-37006d6b5da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639541295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2639541295
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3325543216
Short name T495
Test name
Test status
Simulation time 4061468056 ps
CPU time 63.45 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:47:02 PM PST 23
Peak memory 198812 kb
Host smart-93dd3ed7-78a1-4472-a410-4db8d7aadd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325543216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3325543216
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2981841029
Short name T243
Test name
Test status
Simulation time 1696157930 ps
CPU time 87.99 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:47:26 PM PST 23
Peak memory 198612 kb
Host smart-80024423-6c56-4e4a-97a6-e6841be94727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981841029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2981841029
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1441493575
Short name T344
Test name
Test status
Simulation time 321452105 ps
CPU time 4.01 seconds
Started Dec 24 01:45:54 PM PST 23
Finished Dec 24 01:45:59 PM PST 23
Peak memory 198648 kb
Host smart-ca892590-67ff-4f2d-a738-49e2b83fde7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441493575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1441493575
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.112951662
Short name T505
Test name
Test status
Simulation time 120656636511 ps
CPU time 2105.64 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 02:21:45 PM PST 23
Peak memory 224456 kb
Host smart-91341892-1952-49d1-b031-79a5168b5526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112951662 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.112951662
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.2411563363
Short name T275
Test name
Test status
Simulation time 61116863 ps
CPU time 1.01 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:46:42 PM PST 23
Peak memory 196980 kb
Host smart-683fd8ae-f80a-45c2-aec4-af1e015b0ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411563363 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.2411563363
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3112346456
Short name T382
Test name
Test status
Simulation time 133068594388 ps
CPU time 446.3 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:53:49 PM PST 23
Peak memory 198852 kb
Host smart-cea61b47-9a7a-406d-8ccc-e37456fa1d12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112346456 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3112346456
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2320573888
Short name T441
Test name
Test status
Simulation time 2195782102 ps
CPU time 48.96 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:55 PM PST 23
Peak memory 198832 kb
Host smart-735f478f-c064-472a-8445-cc1595ad4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320573888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2320573888
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3389104945
Short name T317
Test name
Test status
Simulation time 17089336 ps
CPU time 0.63 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 194144 kb
Host smart-9c885a76-ab07-4bc8-aa75-da5d60062c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389104945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3389104945
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2857560745
Short name T240
Test name
Test status
Simulation time 4681970330 ps
CPU time 36.87 seconds
Started Dec 24 01:46:03 PM PST 23
Finished Dec 24 01:46:44 PM PST 23
Peak memory 214864 kb
Host smart-3bc4227e-3e3a-4c9b-aedb-136ff5e01e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857560745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2857560745
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1964910124
Short name T544
Test name
Test status
Simulation time 4269483412 ps
CPU time 33.19 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198848 kb
Host smart-a9ec0d00-7cf8-4614-b33b-3d8eff21f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964910124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1964910124
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2543550708
Short name T617
Test name
Test status
Simulation time 2054066507 ps
CPU time 110.79 seconds
Started Dec 24 01:46:47 PM PST 23
Finished Dec 24 01:48:45 PM PST 23
Peak memory 198596 kb
Host smart-458f4c96-0b52-4d25-81bc-0a6528a220fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543550708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2543550708
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1616076200
Short name T576
Test name
Test status
Simulation time 8372176577 ps
CPU time 35.65 seconds
Started Dec 24 01:46:17 PM PST 23
Finished Dec 24 01:46:54 PM PST 23
Peak memory 198668 kb
Host smart-0569e28e-53fc-4306-8853-cf5392fee145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616076200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1616076200
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.930668204
Short name T211
Test name
Test status
Simulation time 15419900346 ps
CPU time 51.94 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 01:47:40 PM PST 23
Peak memory 198672 kb
Host smart-5c32cb90-1740-43f5-9aa6-e2293694f5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930668204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.930668204
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3191913782
Short name T506
Test name
Test status
Simulation time 395343712 ps
CPU time 3.94 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:46:56 PM PST 23
Peak memory 198456 kb
Host smart-72d7784d-b873-4517-9665-2ec154177c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191913782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3191913782
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4243714807
Short name T765
Test name
Test status
Simulation time 50949744099 ps
CPU time 1150.23 seconds
Started Dec 24 01:46:45 PM PST 23
Finished Dec 24 02:06:03 PM PST 23
Peak memory 198768 kb
Host smart-f0351f76-f081-4359-998f-384e4a5d4359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243714807 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4243714807
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.4162040381
Short name T800
Test name
Test status
Simulation time 234393852705 ps
CPU time 909.78 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 02:00:21 PM PST 23
Peak memory 248068 kb
Host smart-1bc1ceea-ba01-4f05-b112-422120ae027c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162040381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.4162040381
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.965719798
Short name T811
Test name
Test status
Simulation time 167863228 ps
CPU time 0.98 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:20 PM PST 23
Peak memory 196012 kb
Host smart-8d2a6b80-34ec-4d59-803b-8e1f56443b46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965719798 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.965719798
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.4269753971
Short name T520
Test name
Test status
Simulation time 146293471658 ps
CPU time 435.91 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 01:53:55 PM PST 23
Peak memory 198828 kb
Host smart-3e1c6dcc-890f-4a53-8244-79c6e75bda22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269753971 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.4269753971
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1397099398
Short name T480
Test name
Test status
Simulation time 3213273855 ps
CPU time 61.47 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:47:48 PM PST 23
Peak memory 198896 kb
Host smart-00e86f13-5079-4d0d-8893-af1862600dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397099398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1397099398
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.4240385498
Short name T586
Test name
Test status
Simulation time 62588920 ps
CPU time 0.55 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:17 PM PST 23
Peak memory 193112 kb
Host smart-61a62ed7-d3be-412b-b665-ebb9bb0083d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240385498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.4240385498
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1496437658
Short name T831
Test name
Test status
Simulation time 2676237043 ps
CPU time 19.9 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:38 PM PST 23
Peak memory 214284 kb
Host smart-016bbed9-cab1-4e1e-8f87-93351cbb2b1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496437658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1496437658
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2433426364
Short name T341
Test name
Test status
Simulation time 2706333462 ps
CPU time 59.15 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:46:19 PM PST 23
Peak memory 198836 kb
Host smart-b13a54f8-ad99-4db3-83a8-e15e846052b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433426364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2433426364
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1025652730
Short name T618
Test name
Test status
Simulation time 10591581709 ps
CPU time 61.88 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:46:18 PM PST 23
Peak memory 198844 kb
Host smart-e9a9e8c0-39c0-4bab-a42a-937c35220be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025652730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1025652730
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.17053669
Short name T199
Test name
Test status
Simulation time 8215429993 ps
CPU time 127.87 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:47:22 PM PST 23
Peak memory 198816 kb
Host smart-d515ed0b-cf86-4e8c-b02f-65479c997f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17053669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.17053669
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3813676680
Short name T859
Test name
Test status
Simulation time 8698145702 ps
CPU time 75.98 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198860 kb
Host smart-f0e2d852-bd8d-464c-9611-48dcf6cc6fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813676680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3813676680
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2377892838
Short name T832
Test name
Test status
Simulation time 71258457 ps
CPU time 1.79 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:19 PM PST 23
Peak memory 198472 kb
Host smart-0bf20ed8-af6b-4736-9861-b26520bf9124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377892838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2377892838
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1332035039
Short name T581
Test name
Test status
Simulation time 19290962216 ps
CPU time 238.11 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:49:19 PM PST 23
Peak memory 198772 kb
Host smart-70dd51bc-b3b8-4912-8f96-25decf67d23b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332035039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1332035039
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.4031604470
Short name T727
Test name
Test status
Simulation time 400079714886 ps
CPU time 1266.04 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 02:06:25 PM PST 23
Peak memory 256288 kb
Host smart-ea3b8f95-842e-48c8-81f0-df43c09aecbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031604470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.4031604470
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3851601407
Short name T330
Test name
Test status
Simulation time 203900092 ps
CPU time 1.13 seconds
Started Dec 24 01:45:34 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 197140 kb
Host smart-066569c8-7085-4c83-b0f4-0e0faf334818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851601407 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3851601407
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3711057652
Short name T418
Test name
Test status
Simulation time 151623299073 ps
CPU time 464.06 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:53:06 PM PST 23
Peak memory 198888 kb
Host smart-c661cfcf-f211-4a2f-bd1c-3103089f0e0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711057652 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3711057652
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2109517840
Short name T647
Test name
Test status
Simulation time 1462243065 ps
CPU time 17.76 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:35 PM PST 23
Peak memory 198688 kb
Host smart-e8cc8386-bd92-4c78-be74-361ef7bc1262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109517840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2109517840
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3688399383
Short name T475
Test name
Test status
Simulation time 20286902 ps
CPU time 0.56 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 193108 kb
Host smart-89685bba-5241-46df-8f08-6be8c3066fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688399383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3688399383
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3692903532
Short name T426
Test name
Test status
Simulation time 4833635702 ps
CPU time 21.12 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:45:46 PM PST 23
Peak memory 207024 kb
Host smart-2c859200-b8f7-4eee-bda2-0a27d5b15196
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692903532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3692903532
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4016782136
Short name T456
Test name
Test status
Simulation time 6213141507 ps
CPU time 45.16 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:45:59 PM PST 23
Peak memory 198820 kb
Host smart-50d6e640-2259-492f-b1bc-e5a20db5c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016782136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4016782136
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.130407730
Short name T323
Test name
Test status
Simulation time 8546838112 ps
CPU time 122.33 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:47:23 PM PST 23
Peak memory 198840 kb
Host smart-866ca462-3dff-4e04-9a72-eb3e40a9297e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130407730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.130407730
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1204555157
Short name T623
Test name
Test status
Simulation time 26120770122 ps
CPU time 107.51 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:47:02 PM PST 23
Peak memory 198880 kb
Host smart-2276ceab-be23-4f35-93b3-d204c03abdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204555157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1204555157
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3602305971
Short name T605
Test name
Test status
Simulation time 6550239164 ps
CPU time 56.83 seconds
Started Dec 24 01:45:34 PM PST 23
Finished Dec 24 01:46:32 PM PST 23
Peak memory 198900 kb
Host smart-765c0ef6-26f6-4ea9-921d-e0e2e1683ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602305971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3602305971
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.419663135
Short name T458
Test name
Test status
Simulation time 1224904889 ps
CPU time 4.56 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:28 PM PST 23
Peak memory 198708 kb
Host smart-44d87ac5-d199-4e59-aa21-39a645000282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419663135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.419663135
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3109059755
Short name T842
Test name
Test status
Simulation time 19186926832 ps
CPU time 950.09 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 02:01:09 PM PST 23
Peak memory 246052 kb
Host smart-e00fbd29-8eb8-4622-909c-8e2152124faa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109059755 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3109059755
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.1395784359
Short name T359
Test name
Test status
Simulation time 33300660068 ps
CPU time 491.15 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:53:30 PM PST 23
Peak memory 248048 kb
Host smart-322beb82-9e60-4f53-9d62-800a4ed23260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395784359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.1395784359
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.2275052097
Short name T529
Test name
Test status
Simulation time 120611783 ps
CPU time 0.97 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 196408 kb
Host smart-624fb857-c1f8-4587-a080-4d88648be738
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275052097 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.2275052097
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.887517695
Short name T561
Test name
Test status
Simulation time 7847885332 ps
CPU time 364.33 seconds
Started Dec 24 01:45:10 PM PST 23
Finished Dec 24 01:51:16 PM PST 23
Peak memory 198064 kb
Host smart-d0660c11-a54b-49a6-b3e6-c7bfc8612805
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887517695 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.hmac_test_sha_vectors.887517695
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3702669611
Short name T321
Test name
Test status
Simulation time 3093882574 ps
CPU time 57.61 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 198836 kb
Host smart-96a66d67-855a-4927-8344-015006eda3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702669611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3702669611
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3490283321
Short name T788
Test name
Test status
Simulation time 61934969 ps
CPU time 0.57 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 193116 kb
Host smart-5977952c-e573-4100-9da4-9dff66602807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490283321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3490283321
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1302468023
Short name T807
Test name
Test status
Simulation time 1345203378 ps
CPU time 16.76 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:35 PM PST 23
Peak memory 225280 kb
Host smart-6384dee4-7384-4a03-a123-03fcc818ebcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302468023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1302468023
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1833768335
Short name T767
Test name
Test status
Simulation time 6199789371 ps
CPU time 36.45 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:48 PM PST 23
Peak memory 198868 kb
Host smart-f9f4fafe-a76d-4c38-95f5-d6b3aa92fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833768335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1833768335
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3431875823
Short name T809
Test name
Test status
Simulation time 483383269 ps
CPU time 25.33 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:45:49 PM PST 23
Peak memory 198644 kb
Host smart-a2519683-8534-4992-9af0-032dd4f9d888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431875823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3431875823
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.525330688
Short name T642
Test name
Test status
Simulation time 9815591548 ps
CPU time 162.01 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:47:57 PM PST 23
Peak memory 198788 kb
Host smart-03421ad2-916f-4049-9baa-e21d65d8ed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525330688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.525330688
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1634080797
Short name T337
Test name
Test status
Simulation time 1716633598 ps
CPU time 89.52 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:46:49 PM PST 23
Peak memory 198736 kb
Host smart-52dd0119-4f75-4e77-8962-6255c3f5ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634080797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1634080797
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.4057029801
Short name T627
Test name
Test status
Simulation time 221083399 ps
CPU time 2.58 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 198364 kb
Host smart-aebfdcac-c141-4335-b225-1d45b472e0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057029801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4057029801
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2677718817
Short name T632
Test name
Test status
Simulation time 56606504869 ps
CPU time 540.27 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:54:16 PM PST 23
Peak memory 198884 kb
Host smart-d1082e21-e6a5-4cab-bc95-4cd0a3b0e1e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677718817 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2677718817
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.1899651465
Short name T674
Test name
Test status
Simulation time 105828233637 ps
CPU time 1169.73 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 02:04:48 PM PST 23
Peak memory 215248 kb
Host smart-7ccb59e9-a234-4acd-9f32-257944a327df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899651465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.1899651465
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.992741740
Short name T451
Test name
Test status
Simulation time 52957621 ps
CPU time 1.09 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:19 PM PST 23
Peak memory 196928 kb
Host smart-926e7f31-8066-47b0-856b-4c497d174fe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992741740 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.992741740
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2944903076
Short name T834
Test name
Test status
Simulation time 24843624909 ps
CPU time 408.81 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:52:13 PM PST 23
Peak memory 198776 kb
Host smart-de8b6c0e-9128-4d1c-86d3-f7383f9df11c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944903076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2944903076
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2290600767
Short name T493
Test name
Test status
Simulation time 41881854177 ps
CPU time 79.5 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:46:43 PM PST 23
Peak memory 198688 kb
Host smart-099a160a-ce1e-4ad1-8fbe-1da17636b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290600767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2290600767
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3748572551
Short name T39
Test name
Test status
Simulation time 22586361 ps
CPU time 0.63 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:25 PM PST 23
Peak memory 194064 kb
Host smart-707dc679-b19a-4789-87a5-1d88e6e43d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748572551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3748572551
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3368030371
Short name T375
Test name
Test status
Simulation time 946130836 ps
CPU time 7.05 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 198644 kb
Host smart-192ef99c-e412-40eb-91a0-de586b7b00d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3368030371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3368030371
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.783386184
Short name T583
Test name
Test status
Simulation time 7852999034 ps
CPU time 60.71 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:46:19 PM PST 23
Peak memory 197484 kb
Host smart-fdb29e79-7374-4d92-96c2-3ab50949f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783386184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.783386184
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2388850664
Short name T30
Test name
Test status
Simulation time 5832621228 ps
CPU time 73.86 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:46:30 PM PST 23
Peak memory 198784 kb
Host smart-c406630f-90fa-47f9-bd97-54857de0fcea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388850664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2388850664
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.674006865
Short name T615
Test name
Test status
Simulation time 2230197320 ps
CPU time 107.27 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:47:05 PM PST 23
Peak memory 198772 kb
Host smart-2ce00cdb-a03b-479a-83ce-97fa026d052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674006865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.674006865
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3352541778
Short name T331
Test name
Test status
Simulation time 536641517 ps
CPU time 27.57 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:52 PM PST 23
Peak memory 198716 kb
Host smart-0aed67a4-5501-4918-b25a-96cb85027faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352541778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3352541778
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.4283118169
Short name T461
Test name
Test status
Simulation time 374158456 ps
CPU time 1.73 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:45:23 PM PST 23
Peak memory 198428 kb
Host smart-489934e5-22b8-42e7-adec-ec3d8ba5c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283118169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.4283118169
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2954519707
Short name T285
Test name
Test status
Simulation time 133487209 ps
CPU time 3.18 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:28 PM PST 23
Peak memory 198596 kb
Host smart-dec70c71-6108-4dca-bee5-4c8429484d92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954519707 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2954519707
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1124636535
Short name T274
Test name
Test status
Simulation time 108617567 ps
CPU time 1.01 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:21 PM PST 23
Peak memory 197004 kb
Host smart-badf2bde-aa6f-4642-bc86-3fb1d76b644a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124636535 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1124636535
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3042978761
Short name T227
Test name
Test status
Simulation time 26362108637 ps
CPU time 424.29 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:52:22 PM PST 23
Peak memory 198816 kb
Host smart-93a2f670-0726-43da-8eea-f0d3003b0e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042978761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3042978761
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3562755591
Short name T201
Test name
Test status
Simulation time 12665716152 ps
CPU time 18.97 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:39 PM PST 23
Peak memory 198868 kb
Host smart-2218949e-7b60-4106-9960-6a5eec75954e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562755591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3562755591
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.189415876
Short name T558
Test name
Test status
Simulation time 31914786 ps
CPU time 0.57 seconds
Started Dec 24 01:45:40 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 193116 kb
Host smart-b8005c27-f178-4759-94de-3d598f730f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189415876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.189415876
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1815233317
Short name T329
Test name
Test status
Simulation time 1748368957 ps
CPU time 44.7 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 221000 kb
Host smart-a6326986-57bc-433f-a24e-52561a5d6b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815233317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1815233317
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1548740104
Short name T523
Test name
Test status
Simulation time 1570834731 ps
CPU time 8.38 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:45:32 PM PST 23
Peak memory 198716 kb
Host smart-97f91e08-7e5d-4520-9ddd-0a6f5d25f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548740104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1548740104
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2017058938
Short name T309
Test name
Test status
Simulation time 273126464 ps
CPU time 14.34 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:45:54 PM PST 23
Peak memory 198756 kb
Host smart-cd2409d3-f1a1-42d1-ac07-f87ea9ecb48e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017058938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2017058938
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2909107351
Short name T396
Test name
Test status
Simulation time 1874517658 ps
CPU time 22.17 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:02 PM PST 23
Peak memory 198776 kb
Host smart-f3ea4b83-8edd-4803-9994-53d26f5a56c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909107351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2909107351
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3451745371
Short name T282
Test name
Test status
Simulation time 27165272913 ps
CPU time 87.25 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:46:52 PM PST 23
Peak memory 198844 kb
Host smart-c2d9e367-4f7b-4ccd-a377-c3a430a69e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451745371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3451745371
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2956411577
Short name T714
Test name
Test status
Simulation time 228607749 ps
CPU time 2.79 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 01:45:40 PM PST 23
Peak memory 198552 kb
Host smart-07976cfd-618e-47ef-b373-cb62c7bbd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956411577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2956411577
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.923780092
Short name T614
Test name
Test status
Simulation time 4395217585 ps
CPU time 224.57 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:49:24 PM PST 23
Peak memory 198804 kb
Host smart-e10c8b89-e2bc-40d6-aae0-e206c9f94fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923780092 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.923780092
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.3208595340
Short name T126
Test name
Test status
Simulation time 222312140118 ps
CPU time 2456.54 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 02:26:57 PM PST 23
Peak memory 231720 kb
Host smart-a9855251-7ca7-4f01-a802-b8a5a0388466
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208595340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.3208595340
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.2003006638
Short name T261
Test name
Test status
Simulation time 29733620 ps
CPU time 0.94 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 196164 kb
Host smart-23ce250a-0703-4f1c-958c-61f20a3e3573
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003006638 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.2003006638
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.720898421
Short name T388
Test name
Test status
Simulation time 75447818014 ps
CPU time 416.91 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:52:20 PM PST 23
Peak memory 198588 kb
Host smart-c019d93b-dbdb-4485-a6e9-9ab8645fb623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720898421 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_sha_vectors.720898421
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1542734322
Short name T454
Test name
Test status
Simulation time 4916373162 ps
CPU time 51.16 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:14 PM PST 23
Peak memory 198840 kb
Host smart-2379fd2f-1ee3-408f-b424-a9a50f5ed02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542734322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1542734322
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1028552087
Short name T621
Test name
Test status
Simulation time 13722303 ps
CPU time 0.57 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 194120 kb
Host smart-cc06a0a1-90f3-45a2-aba7-ee4619527c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028552087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1028552087
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3559829332
Short name T610
Test name
Test status
Simulation time 6321965454 ps
CPU time 42.26 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:46:40 PM PST 23
Peak memory 214816 kb
Host smart-b6f5d9a6-5bd1-4486-92c9-def87356521e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559829332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3559829332
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.4249338180
Short name T279
Test name
Test status
Simulation time 1094705003 ps
CPU time 48.2 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:46:46 PM PST 23
Peak memory 198712 kb
Host smart-ec29781d-376b-4f14-88c0-cb8d8e18af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249338180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4249338180
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1791761726
Short name T602
Test name
Test status
Simulation time 7743292487 ps
CPU time 95.84 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:47:01 PM PST 23
Peak memory 198872 kb
Host smart-824f75bc-bcc8-43a8-9f0b-a8f7092b2334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791761726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1791761726
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1361125564
Short name T9
Test name
Test status
Simulation time 3216619034 ps
CPU time 44.19 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:46:45 PM PST 23
Peak memory 198804 kb
Host smart-b28d0e3e-1058-43e1-993a-29bf93852b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361125564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1361125564
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3352666509
Short name T644
Test name
Test status
Simulation time 10761000652 ps
CPU time 91.73 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:47:38 PM PST 23
Peak memory 198856 kb
Host smart-e20fe246-32e4-4154-a51c-5a876ab3ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352666509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3352666509
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1414095131
Short name T358
Test name
Test status
Simulation time 673281509 ps
CPU time 1.77 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 01:45:40 PM PST 23
Peak memory 198728 kb
Host smart-55951adb-6358-46e1-9342-c5122b38895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414095131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1414095131
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.633753145
Short name T791
Test name
Test status
Simulation time 6823539754 ps
CPU time 175.26 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:49:03 PM PST 23
Peak memory 198824 kb
Host smart-a14d829d-54ed-490e-ba8c-c67aefbcd01d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633753145 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.633753145
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.16633978
Short name T665
Test name
Test status
Simulation time 71369919268 ps
CPU time 515.7 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:54:42 PM PST 23
Peak memory 208196 kb
Host smart-42124d62-655f-497e-a51d-6951faccb827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16633978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.16633978
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.2841327901
Short name T226
Test name
Test status
Simulation time 33626019 ps
CPU time 1.03 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 196948 kb
Host smart-e7205d07-c4df-4c01-959c-5797dced72cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841327901 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.2841327901
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.2803855397
Short name T659
Test name
Test status
Simulation time 7105446727 ps
CPU time 329.38 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:51:34 PM PST 23
Peak memory 198708 kb
Host smart-e8f59ee9-5bfa-4556-9d12-089ec1d18f3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803855397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.2803855397
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1682530944
Short name T365
Test name
Test status
Simulation time 2692669324 ps
CPU time 17.55 seconds
Started Dec 24 01:45:47 PM PST 23
Finished Dec 24 01:46:05 PM PST 23
Peak memory 198848 kb
Host smart-3b649ca7-e6ef-4064-ab0f-98f4e56232e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682530944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1682530944
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2014992767
Short name T316
Test name
Test status
Simulation time 53981464 ps
CPU time 0.59 seconds
Started Dec 24 01:46:15 PM PST 23
Finished Dec 24 01:46:17 PM PST 23
Peak memory 193052 kb
Host smart-ca7b2fbc-54ae-4916-80c6-ef4e31ba44dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014992767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2014992767
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3872661009
Short name T445
Test name
Test status
Simulation time 2867055999 ps
CPU time 48.53 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:47:28 PM PST 23
Peak memory 227872 kb
Host smart-ce491876-3168-417f-8e71-16b24e3c8d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872661009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3872661009
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1093956842
Short name T232
Test name
Test status
Simulation time 2480005103 ps
CPU time 53.36 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:47:05 PM PST 23
Peak memory 198880 kb
Host smart-1bf8af57-b8ed-4e42-9789-e21e30c9d108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093956842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1093956842
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2841298658
Short name T241
Test name
Test status
Simulation time 372346566 ps
CPU time 9.16 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:31 PM PST 23
Peak memory 198668 kb
Host smart-545a01de-7156-4ef8-abdd-bc7d1ee631f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2841298658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2841298658
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2555932602
Short name T363
Test name
Test status
Simulation time 17556600828 ps
CPU time 50.9 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198768 kb
Host smart-a2d8378b-a024-44de-a0ba-8ecf4a4e9ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555932602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2555932602
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3034969371
Short name T824
Test name
Test status
Simulation time 9334816222 ps
CPU time 129.59 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:49:00 PM PST 23
Peak memory 198828 kb
Host smart-602d985a-bbd6-4c8d-af26-2be0f04dfe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034969371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3034969371
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.688715487
Short name T594
Test name
Test status
Simulation time 149242776 ps
CPU time 1.33 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 197160 kb
Host smart-e5be00d1-464d-422b-85bc-af5d327d63b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688715487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.688715487
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4043971627
Short name T587
Test name
Test status
Simulation time 21266804089 ps
CPU time 147.98 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:49:18 PM PST 23
Peak memory 198820 kb
Host smart-eaef756e-d010-4f55-975d-e11db97cf1bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043971627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4043971627
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.446404696
Short name T609
Test name
Test status
Simulation time 57496405423 ps
CPU time 1381.62 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 02:08:22 PM PST 23
Peak memory 234792 kb
Host smart-d6613c0b-581e-475f-a276-11cadf8ddee4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446404696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.446404696
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3026981774
Short name T713
Test name
Test status
Simulation time 168771917 ps
CPU time 0.88 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 195940 kb
Host smart-cb48c3b8-2cb0-4b18-9759-1aa9ab16d3c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026981774 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3026981774
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2969665090
Short name T355
Test name
Test status
Simulation time 53453422742 ps
CPU time 416.4 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:52:15 PM PST 23
Peak memory 198836 kb
Host smart-5ec2764d-970f-4cae-8deb-3a022d6f06b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969665090 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.2969665090
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1898790240
Short name T203
Test name
Test status
Simulation time 232538283 ps
CPU time 7.99 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:27 PM PST 23
Peak memory 198692 kb
Host smart-2a78bde7-fae7-4886-9a92-91b808fb045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898790240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1898790240
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.986476579
Short name T710
Test name
Test status
Simulation time 45243514 ps
CPU time 0.55 seconds
Started Dec 24 01:45:35 PM PST 23
Finished Dec 24 01:45:37 PM PST 23
Peak memory 193092 kb
Host smart-631e4472-fe56-4eec-8971-63ae6e2a720d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986476579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.986476579
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1990347303
Short name T368
Test name
Test status
Simulation time 266386352 ps
CPU time 7.2 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:45:33 PM PST 23
Peak memory 198732 kb
Host smart-27783b7b-49c8-454c-9d0f-057173629144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990347303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1990347303
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2823615621
Short name T670
Test name
Test status
Simulation time 950304487 ps
CPU time 9.62 seconds
Started Dec 24 01:45:21 PM PST 23
Finished Dec 24 01:45:36 PM PST 23
Peak memory 198724 kb
Host smart-82582fbd-befc-4fdc-b64a-7d6184938d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823615621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2823615621
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.81377361
Short name T230
Test name
Test status
Simulation time 1858126911 ps
CPU time 94.33 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:58 PM PST 23
Peak memory 198532 kb
Host smart-266fc5a5-115d-4929-af9c-7a65988c7216
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81377361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.81377361
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1525726026
Short name T786
Test name
Test status
Simulation time 1632250119 ps
CPU time 14.15 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:45:35 PM PST 23
Peak memory 198748 kb
Host smart-e521b096-1965-4bb8-8213-dc932fb9673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525726026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1525726026
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3151793578
Short name T708
Test name
Test status
Simulation time 6823390759 ps
CPU time 76.82 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198804 kb
Host smart-7166cb0c-51f3-4727-a66b-6590bd09bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151793578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3151793578
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.26125537
Short name T304
Test name
Test status
Simulation time 434284251 ps
CPU time 4.4 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:23 PM PST 23
Peak memory 198600 kb
Host smart-222dc2a2-9f8e-4ce8-aab2-486fea6455c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26125537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.26125537
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3627548113
Short name T613
Test name
Test status
Simulation time 162602831845 ps
CPU time 1275.6 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 02:06:41 PM PST 23
Peak memory 198872 kb
Host smart-953068d1-dc3f-49be-b83f-f907148de450
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627548113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3627548113
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.4240581238
Short name T774
Test name
Test status
Simulation time 372306609855 ps
CPU time 3047.56 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 02:36:07 PM PST 23
Peak memory 263600 kb
Host smart-766038d1-a531-4bd0-a97c-9e69354508ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4240581238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.4240581238
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1286307981
Short name T200
Test name
Test status
Simulation time 25840014 ps
CPU time 0.84 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 195532 kb
Host smart-edf8614a-ead6-43df-8841-9dd1932ba5a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286307981 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1286307981
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.4028407777
Short name T838
Test name
Test status
Simulation time 190983485952 ps
CPU time 430.52 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:52:28 PM PST 23
Peak memory 198884 kb
Host smart-74fcf1e2-6b61-404b-9e94-f16f000d8d33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028407777 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.4028407777
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1914250444
Short name T371
Test name
Test status
Simulation time 206691947 ps
CPU time 3.56 seconds
Started Dec 24 01:45:13 PM PST 23
Finished Dec 24 01:45:22 PM PST 23
Peak memory 198776 kb
Host smart-b2686359-885d-4ffe-8c2c-6a887e2392a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914250444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1914250444
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3586844485
Short name T482
Test name
Test status
Simulation time 60597031 ps
CPU time 0.56 seconds
Started Dec 24 01:44:22 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 193144 kb
Host smart-99a4d89d-eeec-48fb-ad59-ec871ef43775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586844485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3586844485
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2510548357
Short name T679
Test name
Test status
Simulation time 106805500 ps
CPU time 1.21 seconds
Started Dec 24 01:44:27 PM PST 23
Finished Dec 24 01:44:39 PM PST 23
Peak memory 198680 kb
Host smart-6e417ed9-ac76-4c34-9a61-a5f047fae450
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510548357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2510548357
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3323883409
Short name T699
Test name
Test status
Simulation time 1636182300 ps
CPU time 22.03 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:44:58 PM PST 23
Peak memory 198696 kb
Host smart-51dfe3ac-3d6c-44eb-a16c-86a13b2bca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323883409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3323883409
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2829348028
Short name T411
Test name
Test status
Simulation time 6315507419 ps
CPU time 31.22 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:45:05 PM PST 23
Peak memory 198844 kb
Host smart-c9bf2c4f-f6e5-44c4-aebf-01741827a6ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2829348028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2829348028
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1883332394
Short name T745
Test name
Test status
Simulation time 3565779884 ps
CPU time 42.2 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:45:18 PM PST 23
Peak memory 198812 kb
Host smart-c71f8db4-4be1-4f6a-ae00-1e91ede6007e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883332394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1883332394
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1552095216
Short name T748
Test name
Test status
Simulation time 5255417479 ps
CPU time 90.22 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:46:06 PM PST 23
Peak memory 198820 kb
Host smart-fe8cf3df-6be7-4653-9109-e23bdf111786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552095216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1552095216
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1755420506
Short name T46
Test name
Test status
Simulation time 216223114 ps
CPU time 0.97 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 217096 kb
Host smart-71c42e22-c113-4b51-91d6-2d8270cdf48f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755420506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1755420506
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1213102745
Short name T761
Test name
Test status
Simulation time 146802048 ps
CPU time 1.37 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:44:34 PM PST 23
Peak memory 197516 kb
Host smart-50c05776-f5a2-4faa-9fbd-6b5d614612d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213102745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1213102745
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.593041953
Short name T823
Test name
Test status
Simulation time 24713796526 ps
CPU time 278.63 seconds
Started Dec 24 01:44:43 PM PST 23
Finished Dec 24 01:49:22 PM PST 23
Peak memory 231592 kb
Host smart-7646f2e2-cac0-45fa-962d-b80c8b3cc9ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593041953 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.593041953
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.415846978
Short name T374
Test name
Test status
Simulation time 26303232485 ps
CPU time 301.4 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:49:38 PM PST 23
Peak memory 207120 kb
Host smart-8a256e7e-7849-47f1-a9a8-1aa916f30385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415846978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.415846978
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1606275929
Short name T577
Test name
Test status
Simulation time 42793122 ps
CPU time 0.95 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 195828 kb
Host smart-b4ec47dd-9cea-4884-b3c7-93b36e5db88d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606275929 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1606275929
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.667186894
Short name T528
Test name
Test status
Simulation time 8456286323 ps
CPU time 407.68 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:51:20 PM PST 23
Peak memory 198844 kb
Host smart-89b09d19-9001-4532-b528-986c8f88102a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667186894 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.hmac_test_sha_vectors.667186894
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1045069401
Short name T141
Test name
Test status
Simulation time 5455588287 ps
CPU time 45.3 seconds
Started Dec 24 01:44:45 PM PST 23
Finished Dec 24 01:45:32 PM PST 23
Peak memory 198768 kb
Host smart-0fed1dc9-fc5c-4395-9624-467d3f3daf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045069401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1045069401
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1038502076
Short name T350
Test name
Test status
Simulation time 41828385 ps
CPU time 0.6 seconds
Started Dec 24 01:45:40 PM PST 23
Finished Dec 24 01:45:42 PM PST 23
Peak memory 193128 kb
Host smart-085d35c9-1e62-408b-b6ae-f60a02452f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038502076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1038502076
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3945944876
Short name T592
Test name
Test status
Simulation time 1282159145 ps
CPU time 43.21 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 227908 kb
Host smart-fcecd900-f7f3-4dc1-825f-05d51302d385
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3945944876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3945944876
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.4013433235
Short name T464
Test name
Test status
Simulation time 5053161974 ps
CPU time 27.42 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:52 PM PST 23
Peak memory 198840 kb
Host smart-d328ccbb-a8bb-4a55-8577-43bbea72a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013433235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.4013433235
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2924326697
Short name T752
Test name
Test status
Simulation time 99942719 ps
CPU time 5.04 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:27 PM PST 23
Peak memory 198540 kb
Host smart-00fad55f-830f-4376-99ad-e0533b9ff0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924326697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2924326697
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3206296930
Short name T209
Test name
Test status
Simulation time 476489477 ps
CPU time 6.23 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:45:45 PM PST 23
Peak memory 198708 kb
Host smart-00de8d41-cdb7-42ae-b808-d10fa066731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206296930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3206296930
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.542493816
Short name T858
Test name
Test status
Simulation time 20964795529 ps
CPU time 87.53 seconds
Started Dec 24 01:45:41 PM PST 23
Finished Dec 24 01:47:09 PM PST 23
Peak memory 198852 kb
Host smart-de817eaa-ae08-4754-89bd-6815e4c89e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542493816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.542493816
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2469918498
Short name T796
Test name
Test status
Simulation time 1089627417 ps
CPU time 3.91 seconds
Started Dec 24 01:45:21 PM PST 23
Finished Dec 24 01:45:31 PM PST 23
Peak memory 198704 kb
Host smart-d76c4aa7-bd2e-4ba0-a56b-489523f403e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469918498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2469918498
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3363484184
Short name T255
Test name
Test status
Simulation time 306359819209 ps
CPU time 1407.33 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 02:08:53 PM PST 23
Peak memory 217816 kb
Host smart-a6b3801c-ab96-42f4-81e5-b16e4d448f9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363484184 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3363484184
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3131615328
Short name T739
Test name
Test status
Simulation time 102766775364 ps
CPU time 1083.74 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 02:03:44 PM PST 23
Peak memory 215304 kb
Host smart-6596f29c-b086-4882-b388-9185fa1e97ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131615328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.3131615328
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2977887956
Short name T730
Test name
Test status
Simulation time 268052165 ps
CPU time 1.09 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 197248 kb
Host smart-5434adb1-8701-47f3-8d64-dd2440634899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977887956 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2977887956
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1565154920
Short name T224
Test name
Test status
Simulation time 180785866701 ps
CPU time 477.18 seconds
Started Dec 24 01:45:36 PM PST 23
Finished Dec 24 01:53:34 PM PST 23
Peak memory 198800 kb
Host smart-91b36d23-c5be-468a-81c2-be893867ef4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565154920 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1565154920
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2523647628
Short name T277
Test name
Test status
Simulation time 36336568 ps
CPU time 0.58 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 193356 kb
Host smart-ffadfb58-897a-4fb0-b6d6-a44a79e86e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523647628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2523647628
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.239225980
Short name T854
Test name
Test status
Simulation time 12848925 ps
CPU time 0.55 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 193112 kb
Host smart-65c990ce-bf23-400a-924f-af3ec98a2be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239225980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.239225980
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1708312512
Short name T444
Test name
Test status
Simulation time 50114888 ps
CPU time 1.74 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 198212 kb
Host smart-2dbce0cf-efd7-43fd-bfb9-43948102c261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708312512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1708312512
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3718576560
Short name T333
Test name
Test status
Simulation time 10971522304 ps
CPU time 47.07 seconds
Started Dec 24 01:46:33 PM PST 23
Finished Dec 24 01:47:25 PM PST 23
Peak memory 198872 kb
Host smart-e272e55b-626b-465c-b962-b8939c693334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718576560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3718576560
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1235882758
Short name T580
Test name
Test status
Simulation time 1612782630 ps
CPU time 82.79 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:47:24 PM PST 23
Peak memory 198704 kb
Host smart-c387a6ec-09a2-490a-9d1f-4d34e5d3a7a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235882758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1235882758
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3534366736
Short name T378
Test name
Test status
Simulation time 10370501061 ps
CPU time 165.52 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:48:51 PM PST 23
Peak memory 198832 kb
Host smart-50be4d36-1a8e-4a08-805c-916183997c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534366736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3534366736
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2419045153
Short name T636
Test name
Test status
Simulation time 8388647667 ps
CPU time 102.44 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:47:26 PM PST 23
Peak memory 198880 kb
Host smart-4fe4d3f5-5c98-40c4-b028-c864e52c5b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419045153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2419045153
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1525434528
Short name T766
Test name
Test status
Simulation time 125737315 ps
CPU time 2.98 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 198392 kb
Host smart-288af47b-187c-44d3-a842-0ba57d3ffcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525434528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1525434528
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3910962533
Short name T567
Test name
Test status
Simulation time 32870428686 ps
CPU time 823.66 seconds
Started Dec 24 01:45:55 PM PST 23
Finished Dec 24 01:59:40 PM PST 23
Peak memory 215224 kb
Host smart-258f98e6-09aa-44e6-9916-9041e11f51c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910962533 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3910962533
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.1408635845
Short name T369
Test name
Test status
Simulation time 25704208885 ps
CPU time 177.19 seconds
Started Dec 24 01:46:11 PM PST 23
Finished Dec 24 01:49:10 PM PST 23
Peak memory 220484 kb
Host smart-b63c557a-2ced-46b5-8f8a-3473332d93cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408635845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.1408635845
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.398773861
Short name T553
Test name
Test status
Simulation time 97381904 ps
CPU time 0.84 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 195796 kb
Host smart-8743afd7-c927-4840-86d6-96f1bc7d6c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398773861 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.398773861
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1020812724
Short name T814
Test name
Test status
Simulation time 7768411554 ps
CPU time 356.04 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:52:01 PM PST 23
Peak memory 198804 kb
Host smart-94b861bf-0505-4700-a7d0-14f006543712
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020812724 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1020812724
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2194363786
Short name T571
Test name
Test status
Simulation time 1639868749 ps
CPU time 14.5 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 198640 kb
Host smart-c209416f-d5d2-40c8-b746-e8d7ed7d51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194363786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2194363786
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2245270207
Short name T815
Test name
Test status
Simulation time 39556050 ps
CPU time 0.58 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 193096 kb
Host smart-ebd09dbf-88df-4062-9d3e-0837105ccd30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245270207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2245270207
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3823515074
Short name T611
Test name
Test status
Simulation time 2230620579 ps
CPU time 19.09 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:40 PM PST 23
Peak memory 206952 kb
Host smart-3e01dd9c-5e0a-4cfd-83f4-ba3d9b87a117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823515074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3823515074
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2385368680
Short name T262
Test name
Test status
Simulation time 1546655946 ps
CPU time 22.19 seconds
Started Dec 24 01:46:06 PM PST 23
Finished Dec 24 01:46:30 PM PST 23
Peak memory 198756 kb
Host smart-c4d19879-b8c5-493c-b489-6a0efe57437b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385368680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2385368680
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3274241157
Short name T755
Test name
Test status
Simulation time 37235293348 ps
CPU time 115.81 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:48:05 PM PST 23
Peak memory 198848 kb
Host smart-540d831d-30d4-4d2e-b1c9-63cf42f65f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274241157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3274241157
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2137294116
Short name T638
Test name
Test status
Simulation time 2605404956 ps
CPU time 122.22 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:47:45 PM PST 23
Peak memory 198860 kb
Host smart-13cac3b0-dfac-46b3-a32f-683f5d7ffe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137294116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2137294116
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2988327742
Short name T795
Test name
Test status
Simulation time 872484413 ps
CPU time 11.85 seconds
Started Dec 24 01:46:03 PM PST 23
Finished Dec 24 01:46:19 PM PST 23
Peak memory 198712 kb
Host smart-6d59d738-5a8b-4680-bf9f-49e2971b20db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988327742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2988327742
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2589299995
Short name T641
Test name
Test status
Simulation time 539376235 ps
CPU time 3.26 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:46:52 PM PST 23
Peak memory 198760 kb
Host smart-2e0c1c94-7389-4be2-a866-12dd092b0911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589299995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2589299995
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2758408081
Short name T747
Test name
Test status
Simulation time 18875166565 ps
CPU time 823.42 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:59:23 PM PST 23
Peak memory 230680 kb
Host smart-895eced4-8d6f-4697-8e6f-6fcfcd78c5e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758408081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2758408081
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.6088904
Short name T109
Test name
Test status
Simulation time 75490408621 ps
CPU time 3271.66 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 02:40:32 PM PST 23
Peak memory 231576 kb
Host smart-f0c07410-84b2-4c7e-987f-dec161d4067e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6088904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.6088904
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3771591091
Short name T410
Test name
Test status
Simulation time 62849281 ps
CPU time 1.13 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 197952 kb
Host smart-4aa7ef2e-2a9b-4761-a626-d688d8d11da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771591091 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3771591091
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.946935116
Short name T272
Test name
Test status
Simulation time 64373827260 ps
CPU time 454.29 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:53:40 PM PST 23
Peak memory 198804 kb
Host smart-6385374e-573c-454e-9539-4bae36da0260
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946935116 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_sha_vectors.946935116
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.251857743
Short name T706
Test name
Test status
Simulation time 763353802 ps
CPU time 29.3 seconds
Started Dec 24 01:45:32 PM PST 23
Finished Dec 24 01:46:02 PM PST 23
Peak memory 198548 kb
Host smart-a9cc1a27-fdda-4fdc-9ca5-c331e299ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251857743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.251857743
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2027989317
Short name T787
Test name
Test status
Simulation time 12056867 ps
CPU time 0.55 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 193068 kb
Host smart-138ee0a2-8869-4344-bd70-0b18bc34a558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027989317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2027989317
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3235852318
Short name T376
Test name
Test status
Simulation time 73562471 ps
CPU time 1.35 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 198512 kb
Host smart-6f8f8a89-28ee-4e2f-bf69-baf6af87e054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235852318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3235852318
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1993295149
Short name T220
Test name
Test status
Simulation time 5728176179 ps
CPU time 4.57 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 198888 kb
Host smart-d54b5f6f-4397-4e01-8b66-30fb9c549b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993295149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1993295149
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2782421246
Short name T549
Test name
Test status
Simulation time 1671938361 ps
CPU time 42.59 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:46:29 PM PST 23
Peak memory 198712 kb
Host smart-971ffbdc-bd8d-4441-9a46-de0153825c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782421246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2782421246
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.506937810
Short name T569
Test name
Test status
Simulation time 13089825402 ps
CPU time 140.04 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:47:46 PM PST 23
Peak memory 198792 kb
Host smart-27fd11dc-d3c2-4268-b89b-5525f2bd4b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506937810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.506937810
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3775460197
Short name T649
Test name
Test status
Simulation time 19419230073 ps
CPU time 34.93 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 198864 kb
Host smart-df9148f9-3a40-4853-8b63-776ebee10926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775460197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3775460197
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3710462008
Short name T268
Test name
Test status
Simulation time 335707553 ps
CPU time 4.01 seconds
Started Dec 24 01:45:41 PM PST 23
Finished Dec 24 01:45:46 PM PST 23
Peak memory 198740 kb
Host smart-7d6fe764-9578-46bf-86ee-0f5105e0cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710462008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3710462008
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1894164736
Short name T813
Test name
Test status
Simulation time 17885364160 ps
CPU time 848.55 seconds
Started Dec 24 01:45:22 PM PST 23
Finished Dec 24 01:59:37 PM PST 23
Peak memory 233328 kb
Host smart-0739cb74-35bd-4113-9de7-b40c2416092a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894164736 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1894164736
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1001664309
Short name T548
Test name
Test status
Simulation time 261141490557 ps
CPU time 2444.85 seconds
Started Dec 24 01:45:46 PM PST 23
Finished Dec 24 02:26:32 PM PST 23
Peak memory 257156 kb
Host smart-434c2014-ffed-41b9-a20c-7155b2f233db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001664309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1001664309
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.1871448167
Short name T338
Test name
Test status
Simulation time 32029949 ps
CPU time 1.01 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 196780 kb
Host smart-695df3e4-564a-40f2-bfc4-f5d3e8520d62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871448167 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.1871448167
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.3864675434
Short name T575
Test name
Test status
Simulation time 33131630487 ps
CPU time 404.44 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:52:46 PM PST 23
Peak memory 198832 kb
Host smart-10d13e98-4a55-42a8-b480-c640e779ad67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864675434 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.3864675434
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.846937797
Short name T259
Test name
Test status
Simulation time 11600547144 ps
CPU time 38.86 seconds
Started Dec 24 01:45:40 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 198896 kb
Host smart-8833a8bd-7858-4120-af50-6c52fe3f5010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846937797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.846937797
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3153897339
Short name T855
Test name
Test status
Simulation time 77580783 ps
CPU time 0.6 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:24 PM PST 23
Peak memory 194008 kb
Host smart-06907d10-1716-401e-ac55-5963a42a9202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153897339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3153897339
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4081549758
Short name T598
Test name
Test status
Simulation time 1973045172 ps
CPU time 11.04 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:46:09 PM PST 23
Peak memory 215064 kb
Host smart-e027f188-f235-49f6-a9bb-5478006cb9f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081549758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4081549758
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3219000333
Short name T722
Test name
Test status
Simulation time 5595808289 ps
CPU time 62.71 seconds
Started Dec 24 01:45:22 PM PST 23
Finished Dec 24 01:46:31 PM PST 23
Peak memory 198872 kb
Host smart-7150b0f2-27b3-4a0b-bae6-76ce642d2cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219000333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3219000333
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1391988929
Short name T492
Test name
Test status
Simulation time 473692693 ps
CPU time 23.47 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:45:50 PM PST 23
Peak memory 197588 kb
Host smart-2098b487-d99a-4c01-8a4f-def57fdf660e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391988929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1391988929
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2730645480
Short name T777
Test name
Test status
Simulation time 11935166687 ps
CPU time 159.53 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:48:22 PM PST 23
Peak memory 198836 kb
Host smart-cdd1cb43-5436-4338-8bf3-13d6c5173c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730645480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2730645480
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.415694633
Short name T343
Test name
Test status
Simulation time 6430583025 ps
CPU time 81.67 seconds
Started Dec 24 01:45:33 PM PST 23
Finished Dec 24 01:46:56 PM PST 23
Peak memory 198680 kb
Host smart-e4ef7a1f-bf03-4f13-98d4-678b7c841f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415694633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.415694633
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2909320759
Short name T751
Test name
Test status
Simulation time 1305438393 ps
CPU time 3.93 seconds
Started Dec 24 01:45:22 PM PST 23
Finished Dec 24 01:45:32 PM PST 23
Peak memory 198652 kb
Host smart-7a6bb24e-ffdc-48ec-86e1-ddb021343ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909320759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2909320759
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.201921153
Short name T250
Test name
Test status
Simulation time 341877395596 ps
CPU time 1138.21 seconds
Started Dec 24 01:45:37 PM PST 23
Finished Dec 24 02:04:37 PM PST 23
Peak memory 227524 kb
Host smart-33deb54b-7e09-49d0-b763-7a0756ab8407
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201921153 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.201921153
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.620125727
Short name T500
Test name
Test status
Simulation time 39838740387 ps
CPU time 1152.92 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 02:04:54 PM PST 23
Peak memory 200976 kb
Host smart-2b6fa1bb-5317-4e7a-95d2-e6750f4915c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620125727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.620125727
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.1600655173
Short name T737
Test name
Test status
Simulation time 57730962 ps
CPU time 1.04 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:45:26 PM PST 23
Peak memory 196336 kb
Host smart-fe359e86-90a0-4346-8f7b-7f8b63e0e58d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600655173 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.1600655173
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2432659530
Short name T634
Test name
Test status
Simulation time 35255659498 ps
CPU time 431.59 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:52:36 PM PST 23
Peak memory 198844 kb
Host smart-42414f60-57c9-4832-8143-1bc483f887bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432659530 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.2432659530
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4105104387
Short name T324
Test name
Test status
Simulation time 2433270189 ps
CPU time 40.96 seconds
Started Dec 24 01:45:41 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 198860 kb
Host smart-8081be84-81e1-4f2b-8502-c013a0d2b502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105104387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4105104387
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.361278310
Short name T684
Test name
Test status
Simulation time 11839759852 ps
CPU time 43.4 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:46:10 PM PST 23
Peak memory 231644 kb
Host smart-195b87e9-5eaa-405d-8aa2-e41c9c820b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361278310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.361278310
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.4179222000
Short name T762
Test name
Test status
Simulation time 10906466517 ps
CPU time 40.72 seconds
Started Dec 24 01:45:18 PM PST 23
Finished Dec 24 01:46:05 PM PST 23
Peak memory 198892 kb
Host smart-ac95a919-dd57-4026-b01e-db13bbfac0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179222000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.4179222000
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.783239848
Short name T841
Test name
Test status
Simulation time 7373971555 ps
CPU time 72.31 seconds
Started Dec 24 01:45:20 PM PST 23
Finished Dec 24 01:46:39 PM PST 23
Peak memory 198808 kb
Host smart-ccf90f22-fc87-49b0-a035-2a6b66bda91c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783239848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.783239848
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1675241595
Short name T743
Test name
Test status
Simulation time 34142180370 ps
CPU time 111.15 seconds
Started Dec 24 01:45:44 PM PST 23
Finished Dec 24 01:47:36 PM PST 23
Peak memory 198900 kb
Host smart-07992515-42d8-496d-ba59-e7b5c0fd6d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675241595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1675241595
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1638137940
Short name T485
Test name
Test status
Simulation time 12256249748 ps
CPU time 73 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:47:10 PM PST 23
Peak memory 198888 kb
Host smart-e3f039ae-c6e4-4997-a98e-be226823a6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638137940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1638137940
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3092263308
Short name T442
Test name
Test status
Simulation time 236834054 ps
CPU time 1.91 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:45:48 PM PST 23
Peak memory 198744 kb
Host smart-866deceb-4035-4534-9541-52bf74a673a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092263308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3092263308
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2531378503
Short name T821
Test name
Test status
Simulation time 53551508614 ps
CPU time 634.92 seconds
Started Dec 24 01:45:25 PM PST 23
Finished Dec 24 01:56:04 PM PST 23
Peak memory 229516 kb
Host smart-edfdd9db-d293-4659-a8ed-694b56008a4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531378503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2531378503
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.3922274064
Short name T328
Test name
Test status
Simulation time 52684109855 ps
CPU time 641.36 seconds
Started Dec 24 01:45:55 PM PST 23
Finished Dec 24 01:56:37 PM PST 23
Peak memory 209280 kb
Host smart-18c80296-d701-4139-8767-b965be264433
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3922274064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.3922274064
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.2578966473
Short name T785
Test name
Test status
Simulation time 455033478 ps
CPU time 1.14 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 198272 kb
Host smart-480810b5-dc97-4fd6-b9e6-c2cc372cf1e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578966473 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.2578966473
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3126192497
Short name T205
Test name
Test status
Simulation time 14328155776 ps
CPU time 339.42 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:51:18 PM PST 23
Peak memory 198816 kb
Host smart-b1f30af5-e67f-4852-94e6-4f2d1e29acd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126192497 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3126192497
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.177231125
Short name T721
Test name
Test status
Simulation time 1827088850 ps
CPU time 69 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:48 PM PST 23
Peak memory 198728 kb
Host smart-e27e1b63-a8e0-4c66-b830-a4238092c5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177231125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.177231125
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2567325729
Short name T625
Test name
Test status
Simulation time 30668358 ps
CPU time 0.59 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:46:03 PM PST 23
Peak memory 193060 kb
Host smart-fe40041c-35c8-42ac-ad35-e7086cfaf5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567325729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2567325729
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2402919904
Short name T408
Test name
Test status
Simulation time 1581718267 ps
CPU time 18.32 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:46:04 PM PST 23
Peak memory 239268 kb
Host smart-841c5519-72a6-4922-84f8-d9cca527613d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402919904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2402919904
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2929255245
Short name T281
Test name
Test status
Simulation time 2510217608 ps
CPU time 22.45 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:46:02 PM PST 23
Peak memory 198892 kb
Host smart-a64c48b9-df83-4a35-9db5-5ea25430426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929255245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2929255245
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2962708905
Short name T845
Test name
Test status
Simulation time 3907667589 ps
CPU time 100.95 seconds
Started Dec 24 01:45:43 PM PST 23
Finished Dec 24 01:47:24 PM PST 23
Peak memory 198720 kb
Host smart-6cd04cf7-2583-4289-a36d-90aa373a41d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962708905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2962708905
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2029049946
Short name T303
Test name
Test status
Simulation time 1223302614 ps
CPU time 21.21 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:21 PM PST 23
Peak memory 198716 kb
Host smart-a428dbf1-037c-4ebf-a6bc-08bf77b420b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029049946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2029049946
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1837149017
Short name T557
Test name
Test status
Simulation time 488819327 ps
CPU time 25.33 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:04 PM PST 23
Peak memory 198684 kb
Host smart-914be98b-0f3f-471c-8fe9-d11ffa2c94c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837149017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1837149017
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.538466078
Short name T514
Test name
Test status
Simulation time 252807427 ps
CPU time 3.07 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:45:46 PM PST 23
Peak memory 198704 kb
Host smart-a1c1093d-7939-4fda-8a3c-d709948a5e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538466078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.538466078
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2068049701
Short name T812
Test name
Test status
Simulation time 187908252998 ps
CPU time 1198.77 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 02:05:56 PM PST 23
Peak memory 198752 kb
Host smart-0e6f0828-2512-4916-9e10-c6b53462b9f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068049701 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2068049701
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.3359248339
Short name T534
Test name
Test status
Simulation time 81352828112 ps
CPU time 600.82 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:56:05 PM PST 23
Peak memory 239896 kb
Host smart-e3a45649-9885-4bdb-9f04-add7ba643595
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359248339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.3359248339
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2417659418
Short name T629
Test name
Test status
Simulation time 57957350 ps
CPU time 1.1 seconds
Started Dec 24 01:45:25 PM PST 23
Finished Dec 24 01:45:30 PM PST 23
Peak memory 196988 kb
Host smart-c2e26a50-d011-46ca-abe9-f2ef9f802884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417659418 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2417659418
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2937937110
Short name T1
Test name
Test status
Simulation time 50195557375 ps
CPU time 63.24 seconds
Started Dec 24 01:45:22 PM PST 23
Finished Dec 24 01:46:32 PM PST 23
Peak memory 198792 kb
Host smart-7663b592-51ce-45a5-a5d9-ff25b87acee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937937110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2937937110
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.811479274
Short name T677
Test name
Test status
Simulation time 14553594 ps
CPU time 0.56 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:45:43 PM PST 23
Peak memory 193100 kb
Host smart-fe96ec4a-a247-434e-9dd0-dddfe18f4fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811479274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.811479274
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2467953062
Short name T322
Test name
Test status
Simulation time 39094997 ps
CPU time 1.39 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:45:48 PM PST 23
Peak memory 198144 kb
Host smart-311e4cf8-6261-413c-b7e9-c8e9b4a91cbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467953062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2467953062
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.8153116
Short name T260
Test name
Test status
Simulation time 5837768619 ps
CPU time 21.14 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 198888 kb
Host smart-207b0683-2642-44ba-acd8-92d1e4091afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8153116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.8153116
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.208466980
Short name T672
Test name
Test status
Simulation time 5096689476 ps
CPU time 64.4 seconds
Started Dec 24 01:45:25 PM PST 23
Finished Dec 24 01:46:34 PM PST 23
Peak memory 198660 kb
Host smart-fd27c76c-871b-4b82-b56a-a9de86399298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208466980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.208466980
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4094997220
Short name T673
Test name
Test status
Simulation time 10934499572 ps
CPU time 120.76 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:47:40 PM PST 23
Peak memory 198908 kb
Host smart-c08d7fa0-7c67-4a17-8762-b3e394d40b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094997220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4094997220
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2606525651
Short name T207
Test name
Test status
Simulation time 3029281706 ps
CPU time 53.2 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:46:56 PM PST 23
Peak memory 198760 kb
Host smart-2958af25-16b1-45c3-89de-5dc2bb6ffc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606525651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2606525651
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2040278660
Short name T531
Test name
Test status
Simulation time 455607894 ps
CPU time 1.26 seconds
Started Dec 24 01:46:03 PM PST 23
Finished Dec 24 01:46:08 PM PST 23
Peak memory 198304 kb
Host smart-7128f13a-18d7-4379-8c51-62e95c127337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040278660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2040278660
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2532596688
Short name T253
Test name
Test status
Simulation time 67319273333 ps
CPU time 70.32 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:49 PM PST 23
Peak memory 198868 kb
Host smart-2009b630-2ec6-4574-8500-8efd8bfa3d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532596688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2532596688
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_stress_all_with_rand_reset.2047337219
Short name T593
Test name
Test status
Simulation time 96784658923 ps
CPU time 1504.11 seconds
Started Dec 24 01:45:40 PM PST 23
Finished Dec 24 02:10:46 PM PST 23
Peak memory 247692 kb
Host smart-66b2a0e7-1c79-47b6-b494-816dd9b99616
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047337219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all_with_rand_reset.2047337219
Directory /workspace/37.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.3467680037
Short name T792
Test name
Test status
Simulation time 200227677 ps
CPU time 1.17 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:46:03 PM PST 23
Peak memory 197276 kb
Host smart-f866a175-089c-44f5-a217-d914d6845c3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467680037 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.3467680037
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.165109257
Short name T692
Test name
Test status
Simulation time 43593507134 ps
CPU time 56.19 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198780 kb
Host smart-6c779dbd-7a91-4620-a9f8-107cf90fe14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165109257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.165109257
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3126635020
Short name T440
Test name
Test status
Simulation time 21821648 ps
CPU time 0.6 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:46:11 PM PST 23
Peak memory 193996 kb
Host smart-d8e79a13-5906-4125-b811-db6bdad56d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126635020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3126635020
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4268838735
Short name T228
Test name
Test status
Simulation time 2772517691 ps
CPU time 18.24 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 207040 kb
Host smart-95118005-80d3-407c-ba03-4b7f99492278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268838735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4268838735
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3477304032
Short name T853
Test name
Test status
Simulation time 6418019018 ps
CPU time 23.9 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:46:30 PM PST 23
Peak memory 198900 kb
Host smart-bdf36b19-faa8-4a59-b8a9-dcdf08c118b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477304032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3477304032
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3929061795
Short name T31
Test name
Test status
Simulation time 9250679062 ps
CPU time 114.04 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:47:59 PM PST 23
Peak memory 198780 kb
Host smart-56c01b0b-231c-404f-ba6f-3d37f2b49160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929061795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3929061795
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.533438653
Short name T263
Test name
Test status
Simulation time 7824776984 ps
CPU time 133.53 seconds
Started Dec 24 01:45:47 PM PST 23
Finished Dec 24 01:48:02 PM PST 23
Peak memory 198860 kb
Host smart-0fec498e-4ec2-444e-a4e6-88a6b5fb7875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533438653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.533438653
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3600677069
Short name T463
Test name
Test status
Simulation time 932897145 ps
CPU time 44.21 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:46:10 PM PST 23
Peak memory 198736 kb
Host smart-87da7c17-b2eb-4179-9e02-0b3459920ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600677069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3600677069
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1841284680
Short name T620
Test name
Test status
Simulation time 445070023 ps
CPU time 1.88 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:45:48 PM PST 23
Peak memory 198720 kb
Host smart-948660ee-3a4a-4968-93cb-f24bb92aa9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841284680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1841284680
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.861844983
Short name T584
Test name
Test status
Simulation time 2805518313 ps
CPU time 137.08 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:49:01 PM PST 23
Peak memory 198856 kb
Host smart-cd53ad67-b446-412c-b9d5-b734cb3ff5d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861844983 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.861844983
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3711982135
Short name T197
Test name
Test status
Simulation time 100548027 ps
CPU time 0.89 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:46:47 PM PST 23
Peak memory 196072 kb
Host smart-43841370-c89e-4e4d-aa8d-373a72bdf836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711982135 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3711982135
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1068237257
Short name T144
Test name
Test status
Simulation time 33364153037 ps
CPU time 417.34 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:53:02 PM PST 23
Peak memory 198860 kb
Host smart-d22a7f72-0d29-4b47-a983-65cc113e9a55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068237257 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.1068237257
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2784081216
Short name T446
Test name
Test status
Simulation time 16736992741 ps
CPU time 77.89 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:47:16 PM PST 23
Peak memory 198860 kb
Host smart-ae7520dc-8658-43ee-8ffa-f7565ecf3eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784081216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2784081216
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2113498384
Short name T448
Test name
Test status
Simulation time 41406825 ps
CPU time 0.54 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:46:10 PM PST 23
Peak memory 192960 kb
Host smart-e4ee1493-9d3c-443d-b0cc-ac1e46218893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113498384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2113498384
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2122174431
Short name T302
Test name
Test status
Simulation time 2015985960 ps
CPU time 25.51 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 01:47:16 PM PST 23
Peak memory 229344 kb
Host smart-9684cf8a-f1cd-413b-8bf4-09f5a528bc95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122174431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2122174431
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3417139061
Short name T856
Test name
Test status
Simulation time 1836550661 ps
CPU time 31.39 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:46:42 PM PST 23
Peak memory 198732 kb
Host smart-a9dac250-b9ef-4fdb-9c4c-419f6bded12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417139061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3417139061
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2338255056
Short name T799
Test name
Test status
Simulation time 1261747079 ps
CPU time 61.1 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:47:10 PM PST 23
Peak memory 198724 kb
Host smart-35cdf51a-af75-4f7e-bf3e-430ab5c92c5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338255056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2338255056
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1399274066
Short name T249
Test name
Test status
Simulation time 6804326842 ps
CPU time 77.59 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:47:28 PM PST 23
Peak memory 198656 kb
Host smart-d2a1b5f4-ac60-41a7-b856-01404d0fb46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399274066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1399274066
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2506046344
Short name T483
Test name
Test status
Simulation time 513132768 ps
CPU time 28.37 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:34 PM PST 23
Peak memory 198644 kb
Host smart-92e49ed3-297e-4c9b-b4d1-07304509aa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506046344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2506046344
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.678671341
Short name T619
Test name
Test status
Simulation time 1264569390 ps
CPU time 4.39 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:46:45 PM PST 23
Peak memory 198688 kb
Host smart-eab9403e-f5c4-496e-bfc7-39c8c1c043a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678671341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.678671341
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.208485867
Short name T731
Test name
Test status
Simulation time 21182044029 ps
CPU time 163.8 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:49:06 PM PST 23
Peak memory 215160 kb
Host smart-3b02dc36-4257-48ad-aa8e-fe9dba0b0189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208485867 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.208485867
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.1323013967
Short name T130
Test name
Test status
Simulation time 38665136949 ps
CPU time 1663.61 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 02:14:32 PM PST 23
Peak memory 233764 kb
Host smart-6208a626-632f-4c1a-a333-2208ae915e28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323013967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.1323013967
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.4074605815
Short name T254
Test name
Test status
Simulation time 132956958 ps
CPU time 0.87 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 195668 kb
Host smart-849cfdcb-db92-4de3-b3d0-74b9dbac5973
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074605815 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.4074605815
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.388605974
Short name T51
Test name
Test status
Simulation time 14061824487 ps
CPU time 87.59 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:48:18 PM PST 23
Peak memory 198876 kb
Host smart-8cef731d-8797-4784-8b12-bc250fdb6862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388605974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.388605974
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2576966654
Short name T422
Test name
Test status
Simulation time 17652203 ps
CPU time 0.59 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 193020 kb
Host smart-29257960-6de0-44ca-9d5a-6e3c60792dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576966654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2576966654
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.856834315
Short name T397
Test name
Test status
Simulation time 1011728031 ps
CPU time 39.92 seconds
Started Dec 24 01:44:14 PM PST 23
Finished Dec 24 01:45:13 PM PST 23
Peak memory 231680 kb
Host smart-bbe53370-64e1-4caa-b23f-d15d01df0370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=856834315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.856834315
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2130526928
Short name T393
Test name
Test status
Simulation time 2919683868 ps
CPU time 26.28 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:45:02 PM PST 23
Peak memory 198688 kb
Host smart-262a35eb-fdde-49bf-98a0-cb61029dfd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130526928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2130526928
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.4147749931
Short name T372
Test name
Test status
Simulation time 1964870698 ps
CPU time 99.69 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 198716 kb
Host smart-1b0a0098-5b46-4ab7-bf0e-4588a3694b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147749931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.4147749931
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2715830880
Short name T835
Test name
Test status
Simulation time 7594101022 ps
CPU time 87.64 seconds
Started Dec 24 01:44:19 PM PST 23
Finished Dec 24 01:46:03 PM PST 23
Peak memory 198872 kb
Host smart-f4761a8d-8f75-4611-b64e-63348d44e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715830880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2715830880
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3060553955
Short name T680
Test name
Test status
Simulation time 10981019133 ps
CPU time 11.05 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:44:47 PM PST 23
Peak memory 198528 kb
Host smart-7c1b051f-2073-455f-8314-301dda811f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060553955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3060553955
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3614967982
Short name T47
Test name
Test status
Simulation time 65107154 ps
CPU time 0.81 seconds
Started Dec 24 01:44:13 PM PST 23
Finished Dec 24 01:44:33 PM PST 23
Peak memory 215820 kb
Host smart-4e316d37-a07f-4a14-a90b-12339de56741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614967982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3614967982
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.378399344
Short name T398
Test name
Test status
Simulation time 105235693 ps
CPU time 2.76 seconds
Started Dec 24 01:44:20 PM PST 23
Finished Dec 24 01:44:39 PM PST 23
Peak memory 198784 kb
Host smart-448ab06f-a52c-4bc0-986a-1efb921e6569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378399344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.378399344
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.585362303
Short name T450
Test name
Test status
Simulation time 71299626536 ps
CPU time 746.34 seconds
Started Dec 24 01:44:12 PM PST 23
Finished Dec 24 01:56:59 PM PST 23
Peak memory 226400 kb
Host smart-5f45563a-e776-4603-b2cd-0d10b8bd9d78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585362303 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.585362303
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2126643839
Short name T604
Test name
Test status
Simulation time 109900094753 ps
CPU time 1583.59 seconds
Started Dec 24 01:44:15 PM PST 23
Finished Dec 24 02:10:58 PM PST 23
Peak memory 247912 kb
Host smart-5870bc66-83c6-4154-84ab-40343ce18f39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126643839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2126643839
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.4235736906
Short name T741
Test name
Test status
Simulation time 51859738 ps
CPU time 1.06 seconds
Started Dec 24 01:44:29 PM PST 23
Finished Dec 24 01:44:39 PM PST 23
Peak memory 198124 kb
Host smart-26c2a978-0ff8-453e-b4dc-f5f310212c49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235736906 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.4235736906
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.4112921503
Short name T295
Test name
Test status
Simulation time 169454313893 ps
CPU time 378.29 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:50:54 PM PST 23
Peak memory 198816 kb
Host smart-65d18b51-6b8e-4f19-a9cc-f6806e651c71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112921503 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.4112921503
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.531496954
Short name T693
Test name
Test status
Simulation time 1355712391 ps
CPU time 13.03 seconds
Started Dec 24 01:44:19 PM PST 23
Finished Dec 24 01:44:49 PM PST 23
Peak memory 198548 kb
Host smart-7d3ef45d-078e-4cd4-94c7-c932d2c8a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531496954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.531496954
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.352357779
Short name T519
Test name
Test status
Simulation time 12590340 ps
CPU time 0.56 seconds
Started Dec 24 01:45:44 PM PST 23
Finished Dec 24 01:45:46 PM PST 23
Peak memory 193072 kb
Host smart-a54df1a7-0a9a-435f-8812-25d2b55a46d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352357779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.352357779
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.882953960
Short name T542
Test name
Test status
Simulation time 272662170 ps
CPU time 8.37 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:46:54 PM PST 23
Peak memory 206932 kb
Host smart-39461ccd-8170-4c89-a339-dbdf3b2d1f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882953960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.882953960
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.401853167
Short name T345
Test name
Test status
Simulation time 2751494924 ps
CPU time 62.39 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:47:23 PM PST 23
Peak memory 198816 kb
Host smart-a9613d2d-11d0-4597-b323-a800c1749a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401853167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.401853167
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3787064401
Short name T626
Test name
Test status
Simulation time 439968293 ps
CPU time 21.7 seconds
Started Dec 24 01:46:03 PM PST 23
Finished Dec 24 01:46:29 PM PST 23
Peak memory 198644 kb
Host smart-5867153b-f9ed-4595-bfa6-100ddbc9cf59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787064401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3787064401
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1813329103
Short name T507
Test name
Test status
Simulation time 3842019462 ps
CPU time 48.03 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:47:40 PM PST 23
Peak memory 198492 kb
Host smart-b512614f-08d0-4a09-9eaf-d947655b7aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813329103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1813329103
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.687557424
Short name T772
Test name
Test status
Simulation time 10849248699 ps
CPU time 49.85 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:47:12 PM PST 23
Peak memory 198928 kb
Host smart-4fad8046-3e57-45dd-b75f-2c9a72d71f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687557424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.687557424
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3284006097
Short name T499
Test name
Test status
Simulation time 80181208 ps
CPU time 1.47 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 198512 kb
Host smart-07972800-69b1-4b3e-97d1-6c69120982f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284006097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3284006097
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4180244212
Short name T423
Test name
Test status
Simulation time 4432873029 ps
CPU time 192.76 seconds
Started Dec 24 01:46:52 PM PST 23
Finished Dec 24 01:50:11 PM PST 23
Peak memory 223444 kb
Host smart-52d3146b-016f-4c41-95bb-28c489e884e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180244212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4180244212
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.59716672
Short name T477
Test name
Test status
Simulation time 91066190481 ps
CPU time 339.66 seconds
Started Dec 24 01:45:43 PM PST 23
Finished Dec 24 01:51:23 PM PST 23
Peak memory 243064 kb
Host smart-976ea870-208e-42ef-87cb-aa99e213f979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59716672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.59716672
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3931085315
Short name T380
Test name
Test status
Simulation time 58227501 ps
CPU time 1.1 seconds
Started Dec 24 01:46:51 PM PST 23
Finished Dec 24 01:46:59 PM PST 23
Peak memory 197556 kb
Host smart-54168dbb-62a5-48e9-9e15-12a2f694a061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931085315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3931085315
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3955293812
Short name T616
Test name
Test status
Simulation time 14601717485 ps
CPU time 362.96 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:52:47 PM PST 23
Peak memory 198752 kb
Host smart-f7be1ca6-904b-4ce1-bc92-97d708a2d2b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955293812 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.3955293812
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2710389908
Short name T216
Test name
Test status
Simulation time 902959666 ps
CPU time 11.28 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:47:04 PM PST 23
Peak memory 198756 kb
Host smart-b96ef90e-18c6-4c2a-9d52-b4bd31e0933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710389908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2710389908
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3020236580
Short name T547
Test name
Test status
Simulation time 34238325 ps
CPU time 0.55 seconds
Started Dec 24 01:46:03 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 193108 kb
Host smart-11e10088-0c54-4558-9d75-33246a3a39c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020236580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3020236580
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1324118904
Short name T794
Test name
Test status
Simulation time 2251818017 ps
CPU time 38.87 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:37 PM PST 23
Peak memory 219700 kb
Host smart-5fd7e74f-041d-435a-9997-31b7605aba50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324118904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1324118904
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.464293782
Short name T770
Test name
Test status
Simulation time 567616095 ps
CPU time 4.42 seconds
Started Dec 24 01:45:43 PM PST 23
Finished Dec 24 01:45:49 PM PST 23
Peak memory 198760 kb
Host smart-b46aa7c4-7f8b-4a6b-a5e1-91da20d20ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464293782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.464293782
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.697164912
Short name T427
Test name
Test status
Simulation time 4120312295 ps
CPU time 104.36 seconds
Started Dec 24 01:45:46 PM PST 23
Finished Dec 24 01:47:32 PM PST 23
Peak memory 198848 kb
Host smart-89b59758-b07b-48e9-b9dd-e4ab926850fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697164912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.697164912
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1164022604
Short name T703
Test name
Test status
Simulation time 2960411150 ps
CPU time 72.72 seconds
Started Dec 24 01:45:55 PM PST 23
Finished Dec 24 01:47:09 PM PST 23
Peak memory 198912 kb
Host smart-3b56dc31-ac02-4fba-a4d4-1ad8eb3301cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164022604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1164022604
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1638482068
Short name T143
Test name
Test status
Simulation time 2429825520 ps
CPU time 70.33 seconds
Started Dec 24 01:45:19 PM PST 23
Finished Dec 24 01:46:36 PM PST 23
Peak memory 198880 kb
Host smart-a673d334-4380-48a8-818b-12c28482d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638482068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1638482068
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2709302218
Short name T256
Test name
Test status
Simulation time 413843010 ps
CPU time 2.51 seconds
Started Dec 24 01:45:25 PM PST 23
Finished Dec 24 01:45:32 PM PST 23
Peak memory 198416 kb
Host smart-274a353c-6043-4969-99a5-054a24eaf197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709302218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2709302218
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3396405948
Short name T213
Test name
Test status
Simulation time 246658932 ps
CPU time 3.38 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 198532 kb
Host smart-ac01b7b5-f546-4248-81bd-923d0d2e8d23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396405948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3396405948
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2640833215
Short name T105
Test name
Test status
Simulation time 646647573563 ps
CPU time 844.9 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 02:00:08 PM PST 23
Peak memory 215324 kb
Host smart-6097c78c-a2c9-447d-85ae-92ff76894aee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640833215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.2640833215
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3178846884
Short name T700
Test name
Test status
Simulation time 53235870 ps
CPU time 0.9 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:46:04 PM PST 23
Peak memory 195496 kb
Host smart-59f289cc-19b5-439a-b562-c4de20096120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178846884 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3178846884
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1582877532
Short name T744
Test name
Test status
Simulation time 16808032684 ps
CPU time 435.88 seconds
Started Dec 24 01:45:44 PM PST 23
Finished Dec 24 01:53:01 PM PST 23
Peak memory 198804 kb
Host smart-9c327a1f-318a-402c-a245-efcd2c21e974
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582877532 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1582877532
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2089296335
Short name T244
Test name
Test status
Simulation time 315907388 ps
CPU time 5.11 seconds
Started Dec 24 01:45:55 PM PST 23
Finished Dec 24 01:46:01 PM PST 23
Peak memory 198728 kb
Host smart-ed7a190b-43dc-413d-b878-ab0eb545ee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089296335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2089296335
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4221592150
Short name T749
Test name
Test status
Simulation time 11667118 ps
CPU time 0.59 seconds
Started Dec 24 01:46:11 PM PST 23
Finished Dec 24 01:46:14 PM PST 23
Peak memory 193104 kb
Host smart-1953ca04-ec6d-4b86-b619-6bb5ed33a0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221592150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4221592150
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2606146959
Short name T120
Test name
Test status
Simulation time 1762767037 ps
CPU time 65.27 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:47:02 PM PST 23
Peak memory 228420 kb
Host smart-f9a1da55-8ec0-45d6-8935-605dee4914c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606146959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2606146959
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1897225871
Short name T409
Test name
Test status
Simulation time 15831465661 ps
CPU time 29.72 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198704 kb
Host smart-3480aa74-f39a-415a-aed4-fb549f108ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897225871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1897225871
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.872711100
Short name T288
Test name
Test status
Simulation time 17425183 ps
CPU time 0.69 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 193988 kb
Host smart-224fe44a-9b67-4356-a067-17519a1384e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872711100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.872711100
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2574294927
Short name T414
Test name
Test status
Simulation time 3759505229 ps
CPU time 179.44 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:48:57 PM PST 23
Peak memory 198780 kb
Host smart-9cc7b173-9024-4349-9289-9fd228d65d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574294927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2574294927
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1176701588
Short name T773
Test name
Test status
Simulation time 2701090855 ps
CPU time 34.08 seconds
Started Dec 24 01:45:46 PM PST 23
Finished Dec 24 01:46:21 PM PST 23
Peak memory 198720 kb
Host smart-5ec66d68-0e82-4f35-9e18-e3b2234e5458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176701588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1176701588
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2607027131
Short name T206
Test name
Test status
Simulation time 202823153 ps
CPU time 0.97 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:45:59 PM PST 23
Peak memory 197328 kb
Host smart-01908731-3988-4fc9-a844-4352731a4dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607027131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2607027131
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2899534619
Short name T645
Test name
Test status
Simulation time 6541828392 ps
CPU time 70.27 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:47:15 PM PST 23
Peak memory 198872 kb
Host smart-033cd731-0383-4eeb-90c4-f6088de665e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899534619 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2899534619
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.574511483
Short name T346
Test name
Test status
Simulation time 563225484574 ps
CPU time 802.12 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:59:31 PM PST 23
Peak memory 225360 kb
Host smart-eb4276e1-9456-43f2-b3ab-3cc80e4c66bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=574511483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.574511483
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2127889795
Short name T433
Test name
Test status
Simulation time 108370812 ps
CPU time 1.12 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 197016 kb
Host smart-2313930a-e7cf-44d4-9107-604d3c7e5b8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127889795 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2127889795
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.700170514
Short name T847
Test name
Test status
Simulation time 139924027393 ps
CPU time 404.09 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:52:50 PM PST 23
Peak memory 198844 kb
Host smart-b1d85a07-efe4-4caf-8a3f-c85d805f4b66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700170514 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.hmac_test_sha_vectors.700170514
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.74536822
Short name T236
Test name
Test status
Simulation time 4177909124 ps
CPU time 59.71 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:47:21 PM PST 23
Peak memory 198852 kb
Host smart-b758b9ae-bd72-4528-a30c-0a6c4b0db8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74536822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.74536822
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3902603325
Short name T470
Test name
Test status
Simulation time 20716760 ps
CPU time 0.56 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 193052 kb
Host smart-da246efe-ae45-4504-805d-b5d11b3783f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902603325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3902603325
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.397547509
Short name T724
Test name
Test status
Simulation time 470818416 ps
CPU time 7.06 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 01:46:46 PM PST 23
Peak memory 214432 kb
Host smart-a9814ebf-d642-4f43-82f9-b5361fdc2678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397547509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.397547509
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1745526862
Short name T698
Test name
Test status
Simulation time 3548452036 ps
CPU time 39.99 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 01:47:28 PM PST 23
Peak memory 198648 kb
Host smart-09b3a6f6-9dee-40ff-8681-962abc6abb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745526862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1745526862
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.766292061
Short name T36
Test name
Test status
Simulation time 2617960344 ps
CPU time 126.77 seconds
Started Dec 24 01:46:10 PM PST 23
Finished Dec 24 01:48:19 PM PST 23
Peak memory 198660 kb
Host smart-2dd1420d-542b-40f9-90fa-b4eb144855cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=766292061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.766292061
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4279738317
Short name T559
Test name
Test status
Simulation time 37738629526 ps
CPU time 104.57 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:47:55 PM PST 23
Peak memory 198628 kb
Host smart-6d08c38b-4315-4729-a461-cfb0c453062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279738317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4279738317
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2366526794
Short name T421
Test name
Test status
Simulation time 9293402330 ps
CPU time 35.86 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:46:45 PM PST 23
Peak memory 198876 kb
Host smart-608f7a1a-3708-4978-93f6-6eb527b2fb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366526794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2366526794
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.361909732
Short name T310
Test name
Test status
Simulation time 219289264 ps
CPU time 1.45 seconds
Started Dec 24 01:46:07 PM PST 23
Finished Dec 24 01:46:11 PM PST 23
Peak memory 197356 kb
Host smart-8f7e239e-7871-4bb4-9122-c99371e0c0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361909732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.361909732
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.54881289
Short name T332
Test name
Test status
Simulation time 251511308908 ps
CPU time 1461.49 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 02:10:44 PM PST 23
Peak memory 230464 kb
Host smart-bb539393-7805-4ef8-a401-02177bb393c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54881289 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.54881289
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2695041508
Short name T689
Test name
Test status
Simulation time 179357413646 ps
CPU time 656.11 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:57:11 PM PST 23
Peak memory 246056 kb
Host smart-e78506e0-7560-4c1d-978a-256d9c46ecd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695041508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2695041508
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.219657013
Short name T839
Test name
Test status
Simulation time 677384677 ps
CPU time 1.11 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 01:46:52 PM PST 23
Peak memory 197036 kb
Host smart-a5d93d55-15b6-4825-b608-0190cc548f4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219657013 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_hmac_vectors.219657013
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3121211846
Short name T306
Test name
Test status
Simulation time 79912145715 ps
CPU time 429.62 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:53:25 PM PST 23
Peak memory 198788 kb
Host smart-a8fd001f-de2f-4987-8d74-f8996d0d0a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121211846 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.3121211846
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3250608038
Short name T545
Test name
Test status
Simulation time 1084507259 ps
CPU time 18.62 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:24 PM PST 23
Peak memory 198724 kb
Host smart-c88d62e0-a32d-43a1-9187-37f012acc79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250608038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3250608038
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3588918497
Short name T223
Test name
Test status
Simulation time 98287532 ps
CPU time 0.57 seconds
Started Dec 24 01:46:22 PM PST 23
Finished Dec 24 01:46:25 PM PST 23
Peak memory 193084 kb
Host smart-13fdd2f7-8add-47d7-9df7-ad7e409d2cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588918497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3588918497
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.449252912
Short name T2
Test name
Test status
Simulation time 1309894680 ps
CPU time 34.94 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:47:20 PM PST 23
Peak memory 215092 kb
Host smart-a7521420-935e-4693-949c-5afde315c4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449252912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.449252912
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1213617110
Short name T381
Test name
Test status
Simulation time 1531574757 ps
CPU time 67.99 seconds
Started Dec 24 01:45:56 PM PST 23
Finished Dec 24 01:47:05 PM PST 23
Peak memory 198712 kb
Host smart-40922388-24cc-4103-916d-7e7d2dd51e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213617110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1213617110
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1441351773
Short name T518
Test name
Test status
Simulation time 1814050493 ps
CPU time 87.37 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:48:06 PM PST 23
Peak memory 198688 kb
Host smart-29370d8a-66ab-4b1a-994e-2875e7077a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1441351773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1441351773
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.123033721
Short name T676
Test name
Test status
Simulation time 4548140193 ps
CPU time 139.6 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:48:23 PM PST 23
Peak memory 198848 kb
Host smart-26de50c8-a328-49db-8113-85b00c2155c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123033721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.123033721
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1444710357
Short name T218
Test name
Test status
Simulation time 3476950375 ps
CPU time 31.98 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:46:35 PM PST 23
Peak memory 198804 kb
Host smart-bb778fc0-a1f8-44b0-93b6-7a489d428361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444710357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1444710357
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2325587059
Short name T234
Test name
Test status
Simulation time 303437570 ps
CPU time 3.49 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:46:11 PM PST 23
Peak memory 198716 kb
Host smart-136d6da4-340d-4ccd-9e1d-ac2e77dc68e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325587059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2325587059
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3631649542
Short name T119
Test name
Test status
Simulation time 36628104492 ps
CPU time 264.79 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:51:05 PM PST 23
Peak memory 198836 kb
Host smart-fda7a8af-54de-4073-ae9e-e2a93f877642
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631649542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3631649542
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.4052411204
Short name T810
Test name
Test status
Simulation time 104203556822 ps
CPU time 476.81 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:54:03 PM PST 23
Peak memory 225316 kb
Host smart-b59dd436-b90d-4d52-b3ee-dd9b0467d69f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4052411204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.4052411204
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2049566584
Short name T738
Test name
Test status
Simulation time 66878008 ps
CPU time 1.1 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:45:59 PM PST 23
Peak memory 196360 kb
Host smart-d7689261-50b8-475f-93a2-fe44e5b8429a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049566584 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2049566584
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1980346491
Short name T455
Test name
Test status
Simulation time 82468612809 ps
CPU time 455.02 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 198760 kb
Host smart-a7840592-8559-4a10-b8e4-15379e0ff48a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980346491 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.1980346491
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3397595282
Short name T235
Test name
Test status
Simulation time 188173418 ps
CPU time 9.31 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:46:14 PM PST 23
Peak memory 198400 kb
Host smart-44904fc8-9b97-4043-bb48-108a064a3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397595282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3397595282
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.887672210
Short name T484
Test name
Test status
Simulation time 29929909 ps
CPU time 0.57 seconds
Started Dec 24 01:46:33 PM PST 23
Finished Dec 24 01:46:39 PM PST 23
Peak memory 193072 kb
Host smart-fc30506a-d542-450a-9cc3-4a913ae5acb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887672210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.887672210
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1401071934
Short name T502
Test name
Test status
Simulation time 1809334306 ps
CPU time 57.07 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:47:04 PM PST 23
Peak memory 223348 kb
Host smart-704bec98-34ce-4231-98ed-0bd3cf5cd3e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401071934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1401071934
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.133165016
Short name T436
Test name
Test status
Simulation time 2020865614 ps
CPU time 26.89 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:46:31 PM PST 23
Peak memory 198668 kb
Host smart-6d957d4d-5c3c-4a02-8744-096c68ae95d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133165016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.133165016
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.194740569
Short name T221
Test name
Test status
Simulation time 2435778790 ps
CPU time 63.2 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 01:47:41 PM PST 23
Peak memory 198736 kb
Host smart-9216f1cd-87f3-49f0-b8be-d184c4ce9fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194740569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.194740569
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.749998851
Short name T487
Test name
Test status
Simulation time 50171003728 ps
CPU time 225.35 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:49:48 PM PST 23
Peak memory 198884 kb
Host smart-ad3411ec-6461-497d-96d0-553678f92d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749998851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.749998851
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.2231244202
Short name T54
Test name
Test status
Simulation time 148674792 ps
CPU time 8.28 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 198740 kb
Host smart-a1020f67-6c10-491e-9780-ffc566bfb196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231244202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.2231244202
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2716390183
Short name T327
Test name
Test status
Simulation time 266075464 ps
CPU time 3.28 seconds
Started Dec 24 01:45:53 PM PST 23
Finished Dec 24 01:45:57 PM PST 23
Peak memory 198716 kb
Host smart-c9517320-6271-47f4-b9c5-57df285e5bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716390183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2716390183
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2837913398
Short name T597
Test name
Test status
Simulation time 204646200447 ps
CPU time 649.17 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:56:56 PM PST 23
Peak memory 229756 kb
Host smart-21371006-7ada-45ed-9f5e-a1b9153d1629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837913398 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2837913398
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.861315599
Short name T308
Test name
Test status
Simulation time 140682128958 ps
CPU time 1266.94 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 02:07:13 PM PST 23
Peak memory 223492 kb
Host smart-4325bf20-5d9a-4e9d-837f-4e045e0d0cba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861315599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.861315599
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.4078020455
Short name T556
Test name
Test status
Simulation time 60426054 ps
CPU time 1.15 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:06 PM PST 23
Peak memory 196984 kb
Host smart-298f81be-9a1a-401e-a77d-0e07627a29ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078020455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.4078020455
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2042512352
Short name T600
Test name
Test status
Simulation time 7387924312 ps
CPU time 370.28 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 01:52:48 PM PST 23
Peak memory 198844 kb
Host smart-7281831c-99c5-4a8f-a2c2-25892e0a8226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042512352 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.2042512352
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1939435810
Short name T7
Test name
Test status
Simulation time 2931116060 ps
CPU time 42.61 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:49 PM PST 23
Peak memory 198804 kb
Host smart-91468b27-6a60-47da-bb55-b56b0623f073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939435810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1939435810
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1443493980
Short name T533
Test name
Test status
Simulation time 35146935 ps
CPU time 0.6 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:46:41 PM PST 23
Peak memory 193028 kb
Host smart-aee38ef9-cc8f-49a1-908f-d76193766584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443493980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1443493980
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.252712005
Short name T687
Test name
Test status
Simulation time 576390017 ps
CPU time 17.58 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 01:46:56 PM PST 23
Peak memory 206920 kb
Host smart-4d7015ad-9502-43a6-8a60-88cf76900749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252712005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.252712005
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2453853542
Short name T267
Test name
Test status
Simulation time 372243781 ps
CPU time 5.76 seconds
Started Dec 24 01:46:01 PM PST 23
Finished Dec 24 01:46:12 PM PST 23
Peak memory 198712 kb
Host smart-7490d601-9c33-4df4-a14b-2b93c83773e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453853542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2453853542
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.691198051
Short name T660
Test name
Test status
Simulation time 3846302054 ps
CPU time 126.22 seconds
Started Dec 24 01:45:58 PM PST 23
Finished Dec 24 01:48:07 PM PST 23
Peak memory 198828 kb
Host smart-657e9fe3-eb42-482b-96ab-a6ba9227ddd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691198051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.691198051
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.4165167948
Short name T606
Test name
Test status
Simulation time 10365785317 ps
CPU time 121.74 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:48:54 PM PST 23
Peak memory 198904 kb
Host smart-9010c5ed-53b0-47ef-b19e-74474f842431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165167948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.4165167948
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1027604251
Short name T646
Test name
Test status
Simulation time 39625984435 ps
CPU time 114.38 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:47:59 PM PST 23
Peak memory 198772 kb
Host smart-e5423bd4-a50b-4ee6-978e-c517a30f492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027604251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1027604251
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1805816187
Short name T735
Test name
Test status
Simulation time 41548263 ps
CPU time 0.89 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 196604 kb
Host smart-4aca171e-49b7-41dd-aed4-e1e35cc7068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805816187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1805816187
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1578445789
Short name T29
Test name
Test status
Simulation time 35288567152 ps
CPU time 1670.47 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 02:14:12 PM PST 23
Peak memory 238804 kb
Host smart-2794df6b-6984-4dbe-8172-55e0657a2d3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578445789 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1578445789
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.2271066845
Short name T717
Test name
Test status
Simulation time 250054825351 ps
CPU time 927.19 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 02:02:05 PM PST 23
Peak memory 239896 kb
Host smart-47ac0528-2515-47aa-aff2-240681198db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2271066845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.2271066845
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1837626603
Short name T572
Test name
Test status
Simulation time 1006122219 ps
CPU time 1.2 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:06 PM PST 23
Peak memory 197760 kb
Host smart-10006965-b23b-427e-b13d-e9f04dba1b03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837626603 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1837626603
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1232398316
Short name T510
Test name
Test status
Simulation time 25843997065 ps
CPU time 400.97 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:52:52 PM PST 23
Peak memory 198812 kb
Host smart-d89a4852-806f-43e1-9ee7-f502ebe5b72b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232398316 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.1232398316
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3934009636
Short name T655
Test name
Test status
Simulation time 912201018 ps
CPU time 22.53 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:46:45 PM PST 23
Peak memory 198716 kb
Host smart-32547e07-bda5-4f3d-bc1e-12d6d2997455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934009636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3934009636
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2933284072
Short name T38
Test name
Test status
Simulation time 12770833 ps
CPU time 0.57 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 192952 kb
Host smart-f30e584a-7586-4f12-a4e6-1887ef2a399e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933284072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2933284072
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2517217026
Short name T49
Test name
Test status
Simulation time 1158664355 ps
CPU time 10.66 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:47:03 PM PST 23
Peak memory 214452 kb
Host smart-4834e3d9-7f79-416a-b68e-3b3083c5e223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517217026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2517217026
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1627173701
Short name T702
Test name
Test status
Simulation time 1335253034 ps
CPU time 29.65 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198728 kb
Host smart-8565342a-9c34-4c89-8706-814ddeb4ab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627173701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1627173701
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3859982802
Short name T367
Test name
Test status
Simulation time 683414875 ps
CPU time 19.63 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:47:08 PM PST 23
Peak memory 198668 kb
Host smart-6426505c-b012-4428-9bef-b06c73ce958e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859982802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3859982802
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1041688171
Short name T449
Test name
Test status
Simulation time 15860040473 ps
CPU time 253.48 seconds
Started Dec 24 01:46:11 PM PST 23
Finished Dec 24 01:50:26 PM PST 23
Peak memory 198844 kb
Host smart-70c1eccb-9e0a-4ed3-872b-df67344b0bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041688171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1041688171
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4029900763
Short name T671
Test name
Test status
Simulation time 1744396419 ps
CPU time 8.3 seconds
Started Dec 24 01:46:08 PM PST 23
Finished Dec 24 01:46:18 PM PST 23
Peak memory 198752 kb
Host smart-d696a470-a7f5-4e74-8e72-7a4a94501641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029900763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4029900763
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3811764834
Short name T314
Test name
Test status
Simulation time 102906665 ps
CPU time 0.87 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:46:12 PM PST 23
Peak memory 195904 kb
Host smart-b7ef76fe-e182-4760-8c2f-0ff862e86c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811764834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3811764834
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2880460867
Short name T390
Test name
Test status
Simulation time 9959440733 ps
CPU time 506.88 seconds
Started Dec 24 01:45:59 PM PST 23
Finished Dec 24 01:54:31 PM PST 23
Peak memory 198840 kb
Host smart-b60ef243-9c99-4dbe-9c6b-f1d99b21f3ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880460867 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2880460867
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.2097536075
Short name T535
Test name
Test status
Simulation time 91158832130 ps
CPU time 1377.24 seconds
Started Dec 24 01:46:11 PM PST 23
Finished Dec 24 02:09:10 PM PST 23
Peak memory 247952 kb
Host smart-5a512b75-9d74-4d87-bf53-ce9941bad1c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097536075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.2097536075
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2722004846
Short name T204
Test name
Test status
Simulation time 79048722 ps
CPU time 0.94 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 195524 kb
Host smart-503acaa2-646e-467e-a461-a3fa413d9d0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722004846 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2722004846
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2596599976
Short name T311
Test name
Test status
Simulation time 17617640048 ps
CPU time 405.54 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:53:35 PM PST 23
Peak memory 198832 kb
Host smart-7c6d2054-1524-4127-b003-ff3f12f10657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596599976 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2596599976
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2024694143
Short name T290
Test name
Test status
Simulation time 3572121283 ps
CPU time 40.1 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 01:47:18 PM PST 23
Peak memory 198744 kb
Host smart-8bb8d443-7284-402d-af20-ea887276b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024694143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2024694143
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3196284698
Short name T417
Test name
Test status
Simulation time 23902777 ps
CPU time 0.57 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 193980 kb
Host smart-1b4873b4-9381-4725-ba9c-f60e7f7ec18d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196284698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3196284698
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2076435442
Short name T33
Test name
Test status
Simulation time 3464840959 ps
CPU time 26.74 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:48 PM PST 23
Peak memory 215068 kb
Host smart-6110dd66-acc0-44da-8441-8d1d760d35b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076435442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2076435442
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.273407046
Short name T683
Test name
Test status
Simulation time 355697756 ps
CPU time 4.19 seconds
Started Dec 24 01:46:06 PM PST 23
Finished Dec 24 01:46:13 PM PST 23
Peak memory 198712 kb
Host smart-8f02df88-9905-4726-9a07-bad0d63e9955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273407046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.273407046
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.673719771
Short name T837
Test name
Test status
Simulation time 2120534807 ps
CPU time 15.63 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:21 PM PST 23
Peak memory 198656 kb
Host smart-c314f7cc-e943-4cdb-9c6c-c6aa67e29074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=673719771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.673719771
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3871146484
Short name T325
Test name
Test status
Simulation time 8514787643 ps
CPU time 18.78 seconds
Started Dec 24 01:46:10 PM PST 23
Finished Dec 24 01:46:30 PM PST 23
Peak memory 198848 kb
Host smart-ff5d4114-0a3f-4258-bebc-eb9c8ded4d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871146484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3871146484
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3863419660
Short name T399
Test name
Test status
Simulation time 21673850048 ps
CPU time 64.32 seconds
Started Dec 24 01:46:37 PM PST 23
Finished Dec 24 01:47:50 PM PST 23
Peak memory 198764 kb
Host smart-c758497c-0159-46b4-a6e0-1d0901b32528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863419660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3863419660
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3483719319
Short name T759
Test name
Test status
Simulation time 149822802 ps
CPU time 0.89 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 01:46:23 PM PST 23
Peak memory 195612 kb
Host smart-83ac52df-f80f-49b7-b3c7-70b44bb4a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483719319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3483719319
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2186181202
Short name T734
Test name
Test status
Simulation time 29951312213 ps
CPU time 498.21 seconds
Started Dec 24 01:46:35 PM PST 23
Finished Dec 24 01:54:57 PM PST 23
Peak memory 198868 kb
Host smart-8c09913a-f500-4dd9-bde8-e226dbc89c0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186181202 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2186181202
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_stress_all_with_rand_reset.1890086413
Short name T238
Test name
Test status
Simulation time 367625974575 ps
CPU time 1540.87 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 02:12:19 PM PST 23
Peak memory 257124 kb
Host smart-ab182fd5-7bd6-433f-bdfe-9c8bcc73a91d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890086413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all_with_rand_reset.1890086413
Directory /workspace/48.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2204098527
Short name T652
Test name
Test status
Simulation time 109276416 ps
CPU time 1.07 seconds
Started Dec 24 01:46:09 PM PST 23
Finished Dec 24 01:46:12 PM PST 23
Peak memory 196748 kb
Host smart-ecae7716-4a25-4a82-9760-bdc8d8410373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204098527 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2204098527
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2419294814
Short name T769
Test name
Test status
Simulation time 52117673432 ps
CPU time 364.07 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 01:52:52 PM PST 23
Peak memory 198772 kb
Host smart-fa2ff7ef-1f46-4576-8050-4f5f0a8fa556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419294814 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.2419294814
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1968441879
Short name T339
Test name
Test status
Simulation time 1698097776 ps
CPU time 16.51 seconds
Started Dec 24 01:46:10 PM PST 23
Finished Dec 24 01:46:28 PM PST 23
Peak memory 198552 kb
Host smart-fddcbbd3-159d-4188-a5d2-55d7c8c9ec27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968441879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1968441879
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2859968372
Short name T214
Test name
Test status
Simulation time 36283242 ps
CPU time 0.55 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:46:16 PM PST 23
Peak memory 193020 kb
Host smart-fca1b227-4630-4eef-91cd-ad2536b88271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859968372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2859968372
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2331119835
Short name T550
Test name
Test status
Simulation time 201647624 ps
CPU time 5.7 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:46:13 PM PST 23
Peak memory 215068 kb
Host smart-598b15af-1e63-483e-9830-88cc6926f5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331119835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2331119835
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2763012607
Short name T289
Test name
Test status
Simulation time 2370030845 ps
CPU time 39.74 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 01:47:30 PM PST 23
Peak memory 198784 kb
Host smart-762606e4-b8b0-4fb8-bfb9-b1eca79dd1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763012607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2763012607
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3751709356
Short name T570
Test name
Test status
Simulation time 4267153303 ps
CPU time 110.02 seconds
Started Dec 24 01:46:49 PM PST 23
Finished Dec 24 01:48:47 PM PST 23
Peak memory 198840 kb
Host smart-0be4a822-8b8b-4da5-8b93-e3049a5e33c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3751709356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3751709356
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2252807389
Short name T286
Test name
Test status
Simulation time 65766356996 ps
CPU time 84.88 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 01:48:15 PM PST 23
Peak memory 198852 kb
Host smart-f81eb504-9396-4d8d-a2f5-fdcc3c66c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252807389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2252807389
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.4138865464
Short name T525
Test name
Test status
Simulation time 3812446804 ps
CPU time 35.19 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:47:25 PM PST 23
Peak memory 198816 kb
Host smart-d58c0b5b-787b-446c-a84c-403928667846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138865464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.4138865464
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4257928791
Short name T453
Test name
Test status
Simulation time 94480920 ps
CPU time 1.57 seconds
Started Dec 24 01:46:04 PM PST 23
Finished Dec 24 01:46:09 PM PST 23
Peak memory 198472 kb
Host smart-4bf038ac-3695-4ada-838a-6e10024cd75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257928791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4257928791
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.262050383
Short name T107
Test name
Test status
Simulation time 108939142673 ps
CPU time 1587.26 seconds
Started Dec 24 01:46:47 PM PST 23
Finished Dec 24 02:13:22 PM PST 23
Peak memory 198732 kb
Host smart-f7c64678-1af7-4d75-9907-e6167982ab49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262050383 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.262050383
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.4293179672
Short name T415
Test name
Test status
Simulation time 265014575 ps
CPU time 1.1 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:46:53 PM PST 23
Peak memory 196372 kb
Host smart-2aecccd1-a931-42fd-9d42-8610e282f11c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293179672 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.4293179672
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.736930589
Short name T237
Test name
Test status
Simulation time 111531921934 ps
CPU time 451.74 seconds
Started Dec 24 01:46:42 PM PST 23
Finished Dec 24 01:54:24 PM PST 23
Peak memory 198776 kb
Host smart-4203e824-69f5-4f5c-b569-19133eb501f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736930589 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_test_sha_vectors.736930589
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1034584171
Short name T349
Test name
Test status
Simulation time 2866060917 ps
CPU time 12.26 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:47:04 PM PST 23
Peak memory 198804 kb
Host smart-fc8b4302-43b7-4701-8e33-6b6fde66522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034584171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1034584171
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.694247477
Short name T829
Test name
Test status
Simulation time 11388194 ps
CPU time 0.61 seconds
Started Dec 24 01:44:31 PM PST 23
Finished Dec 24 01:44:38 PM PST 23
Peak memory 193112 kb
Host smart-f7bdd9bb-6b6e-43e7-a902-113ebc226b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694247477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.694247477
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.703474537
Short name T55
Test name
Test status
Simulation time 207891398 ps
CPU time 6.44 seconds
Started Dec 24 01:44:26 PM PST 23
Finished Dec 24 01:44:43 PM PST 23
Peak memory 198792 kb
Host smart-1a555185-a47b-4365-8b66-9e228c6f635c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703474537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.703474537
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2809039207
Short name T357
Test name
Test status
Simulation time 4737208148 ps
CPU time 17.28 seconds
Started Dec 24 01:44:40 PM PST 23
Finished Dec 24 01:44:58 PM PST 23
Peak memory 198880 kb
Host smart-f9482b3d-7ef7-41e8-aa42-79e43e1737d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809039207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2809039207
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.948079280
Short name T509
Test name
Test status
Simulation time 2694045790 ps
CPU time 133.31 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:48:06 PM PST 23
Peak memory 198404 kb
Host smart-8b5d2b80-484f-4a01-834e-52bbbecaee0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948079280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.948079280
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2415632333
Short name T711
Test name
Test status
Simulation time 2790795313 ps
CPU time 137.81 seconds
Started Dec 24 01:44:25 PM PST 23
Finished Dec 24 01:46:55 PM PST 23
Peak memory 198640 kb
Host smart-0816e569-c007-4454-a0a8-5a013be380f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415632333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2415632333
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2295133266
Short name T720
Test name
Test status
Simulation time 46800398493 ps
CPU time 67.06 seconds
Started Dec 24 01:44:24 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 198748 kb
Host smart-b5616280-bee3-488c-a9e4-d9c1354b7611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295133266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2295133266
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3447061275
Short name T697
Test name
Test status
Simulation time 1313069797 ps
CPU time 1.75 seconds
Started Dec 24 01:44:17 PM PST 23
Finished Dec 24 01:44:36 PM PST 23
Peak memory 198260 kb
Host smart-4dc6d5e6-636c-432a-84f9-846866773cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447061275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3447061275
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.472240670
Short name T318
Test name
Test status
Simulation time 3249238115 ps
CPU time 59.46 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:46:52 PM PST 23
Peak memory 222292 kb
Host smart-2509172f-6734-42fc-b0d1-12cc1c41176c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472240670 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.472240670
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3545481403
Short name T198
Test name
Test status
Simulation time 164730844276 ps
CPU time 551.95 seconds
Started Dec 24 01:44:08 PM PST 23
Finished Dec 24 01:53:39 PM PST 23
Peak memory 210824 kb
Host smart-b8241be6-d9f3-4942-8b1c-5dc867a5c0fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3545481403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3545481403
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3870696568
Short name T828
Test name
Test status
Simulation time 58001958 ps
CPU time 1.19 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:44:37 PM PST 23
Peak memory 197244 kb
Host smart-8a52ff25-47f0-437b-892e-4cafc8c51bd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870696568 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3870696568
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2694612703
Short name T498
Test name
Test status
Simulation time 8806417194 ps
CPU time 92.08 seconds
Started Dec 24 01:45:35 PM PST 23
Finished Dec 24 01:47:09 PM PST 23
Peak memory 197532 kb
Host smart-a1873fe7-b3fb-4876-b781-d909ae7261cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694612703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2694612703
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.962610835
Short name T88
Test name
Test status
Simulation time 112591019205 ps
CPU time 1419.44 seconds
Started Dec 24 01:46:15 PM PST 23
Finished Dec 24 02:09:56 PM PST 23
Peak memory 215244 kb
Host smart-4687ab4c-cd69-417f-961a-be6f13ad9e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962610835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.962610835
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.1522396410
Short name T90
Test name
Test status
Simulation time 1251811152323 ps
CPU time 4877.42 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 03:08:10 PM PST 23
Peak memory 272248 kb
Host smart-89cc92e1-641c-47d9-b695-d47c31ecfa36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522396410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.1522396410
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.789936773
Short name T701
Test name
Test status
Simulation time 57381550889 ps
CPU time 877.27 seconds
Started Dec 24 01:46:42 PM PST 23
Finished Dec 24 02:01:29 PM PST 23
Peak memory 215276 kb
Host smart-85c8093f-c232-492a-b17f-d57f93b921ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789936773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.789936773
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.2255648835
Short name T657
Test name
Test status
Simulation time 63194363088 ps
CPU time 1623.61 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 02:13:54 PM PST 23
Peak memory 218756 kb
Host smart-b9d302dc-f13f-4350-8ebf-cfac6aa18b67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2255648835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.2255648835
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.2958814075
Short name T808
Test name
Test status
Simulation time 181028912028 ps
CPU time 662.2 seconds
Started Dec 24 01:46:47 PM PST 23
Finished Dec 24 01:57:57 PM PST 23
Peak memory 247708 kb
Host smart-4527c3db-c2bd-4dd1-9d59-93d5bf1f8c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2958814075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.2958814075
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.286196657
Short name T473
Test name
Test status
Simulation time 202530931542 ps
CPU time 869.37 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:01:22 PM PST 23
Peak memory 238528 kb
Host smart-dadd09a6-7958-42f7-be50-e4c7a6643891
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286196657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.286196657
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.4209521862
Short name T522
Test name
Test status
Simulation time 135154294650 ps
CPU time 1795.8 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 02:16:12 PM PST 23
Peak memory 263352 kb
Host smart-45345b62-a52f-4802-a0f8-462b099cb333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209521862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.4209521862
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.965712362
Short name T568
Test name
Test status
Simulation time 434931702864 ps
CPU time 1298.9 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 02:08:31 PM PST 23
Peak memory 247712 kb
Host smart-7cb28feb-a685-43bd-b66b-d588d7985b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965712362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.965712362
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.hmac_stress_all_with_rand_reset.139773166
Short name T353
Test name
Test status
Simulation time 2061873386 ps
CPU time 105.77 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:48:38 PM PST 23
Peak memory 198560 kb
Host smart-0ccaf0e4-43db-40ad-b570-a0964f442e8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139773166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.hmac_stress_all_with_rand_reset.139773166
Directory /workspace/59.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.842623116
Short name T750
Test name
Test status
Simulation time 68417344 ps
CPU time 0.58 seconds
Started Dec 24 01:45:09 PM PST 23
Finished Dec 24 01:45:11 PM PST 23
Peak memory 193180 kb
Host smart-2d2f986c-ffb6-4ab2-a7fe-1300498acd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842623116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.842623116
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3800201991
Short name T284
Test name
Test status
Simulation time 1053562772 ps
CPU time 16.53 seconds
Started Dec 24 01:44:31 PM PST 23
Finished Dec 24 01:44:54 PM PST 23
Peak memory 206872 kb
Host smart-4c17ddc9-5a72-4461-9be3-97a87f26b2c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800201991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3800201991
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4294259954
Short name T603
Test name
Test status
Simulation time 72580103 ps
CPU time 3.18 seconds
Started Dec 24 01:44:39 PM PST 23
Finished Dec 24 01:44:43 PM PST 23
Peak memory 198740 kb
Host smart-92b76d4e-0209-44cd-bce4-c36aec33bac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294259954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4294259954
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2291486071
Short name T239
Test name
Test status
Simulation time 7004766285 ps
CPU time 85.13 seconds
Started Dec 24 01:45:52 PM PST 23
Finished Dec 24 01:47:18 PM PST 23
Peak memory 198392 kb
Host smart-6bba93d7-757a-4574-85cb-13a85ef05750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291486071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2291486071
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3875650348
Short name T202
Test name
Test status
Simulation time 10115832324 ps
CPU time 118.79 seconds
Started Dec 24 01:45:35 PM PST 23
Finished Dec 24 01:47:36 PM PST 23
Peak memory 197564 kb
Host smart-6678d7fe-df5d-44a1-a28d-e19ed7126c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875650348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3875650348
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.482368580
Short name T725
Test name
Test status
Simulation time 9864383986 ps
CPU time 60.39 seconds
Started Dec 24 01:45:50 PM PST 23
Finished Dec 24 01:46:52 PM PST 23
Peak memory 198108 kb
Host smart-91a4eccd-f0f6-4e8f-b9ce-6f6f01ef3a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482368580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.482368580
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2589861261
Short name T489
Test name
Test status
Simulation time 292263706 ps
CPU time 1.31 seconds
Started Dec 24 01:44:37 PM PST 23
Finished Dec 24 01:44:40 PM PST 23
Peak memory 197616 kb
Host smart-a504b32f-c7c8-49eb-8a73-85837a8e9e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589861261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2589861261
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1137657192
Short name T667
Test name
Test status
Simulation time 37301822574 ps
CPU time 401.34 seconds
Started Dec 24 01:44:58 PM PST 23
Finished Dec 24 01:51:40 PM PST 23
Peak memory 198788 kb
Host smart-347c39cb-7810-4909-98cb-c8d5b5afb743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137657192 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1137657192
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.3203569403
Short name T245
Test name
Test status
Simulation time 304587958606 ps
CPU time 1316.23 seconds
Started Dec 24 01:44:48 PM PST 23
Finished Dec 24 02:06:45 PM PST 23
Peak memory 263728 kb
Host smart-2182d1b1-e12e-40f3-b88d-e642e04adddc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203569403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.3203569403
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2466135771
Short name T654
Test name
Test status
Simulation time 55559812 ps
CPU time 1.18 seconds
Started Dec 24 01:45:01 PM PST 23
Finished Dec 24 01:45:03 PM PST 23
Peak memory 197068 kb
Host smart-94af199b-b59f-4fc8-a19f-088160dbe14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466135771 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2466135771
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3962783323
Short name T640
Test name
Test status
Simulation time 29153831144 ps
CPU time 451.22 seconds
Started Dec 24 01:45:50 PM PST 23
Finished Dec 24 01:53:23 PM PST 23
Peak memory 198404 kb
Host smart-6477c1b1-c008-4e58-b2d6-728d07d0742a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962783323 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.3962783323
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2674727057
Short name T601
Test name
Test status
Simulation time 15728479688 ps
CPU time 56.79 seconds
Started Dec 24 01:44:21 PM PST 23
Finished Dec 24 01:45:33 PM PST 23
Peak memory 198752 kb
Host smart-061fe70d-bf84-4d4d-94d0-46c1e0823775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674727057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2674727057
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.1572723826
Short name T705
Test name
Test status
Simulation time 549302185493 ps
CPU time 5585.18 seconds
Started Dec 24 01:46:49 PM PST 23
Finished Dec 24 03:20:03 PM PST 23
Peak memory 264200 kb
Host smart-b629af3e-14d7-490a-ab26-65af6fdbdae0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572723826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.1572723826
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.932794494
Short name T138
Test name
Test status
Simulation time 51300367282 ps
CPU time 2246.63 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 02:24:15 PM PST 23
Peak memory 244856 kb
Host smart-c3cbd6b0-96a8-4635-8655-a0f04f3c3dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932794494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.932794494
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.426250514
Short name T803
Test name
Test status
Simulation time 17029885936 ps
CPU time 82.59 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:47:38 PM PST 23
Peak memory 215104 kb
Host smart-48819d26-d6be-45b5-9e2d-4cf293950e23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426250514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.426250514
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.1131569334
Short name T431
Test name
Test status
Simulation time 192995285752 ps
CPU time 807.8 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 02:00:15 PM PST 23
Peak memory 242252 kb
Host smart-efda048b-037d-40aa-b262-ce54c6b42dfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1131569334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.1131569334
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.2556356312
Short name T469
Test name
Test status
Simulation time 129494078035 ps
CPU time 676.21 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:57:32 PM PST 23
Peak memory 244060 kb
Host smart-9a83cb25-2a93-4473-9ec8-053c073ee45e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2556356312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.2556356312
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.1251995021
Short name T851
Test name
Test status
Simulation time 1112526863313 ps
CPU time 2050.61 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 02:21:03 PM PST 23
Peak memory 260488 kb
Host smart-652a8da1-7a59-4845-b786-91b49d64b1a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1251995021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.1251995021
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3597628932
Short name T271
Test name
Test status
Simulation time 78200303411 ps
CPU time 217.52 seconds
Started Dec 24 01:46:20 PM PST 23
Finished Dec 24 01:50:00 PM PST 23
Peak memory 243524 kb
Host smart-54f2256c-bb24-4ee6-a935-a2e13c95855a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597628932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3597628932
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.3239199252
Short name T844
Test name
Test status
Simulation time 83618422187 ps
CPU time 412.79 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:53:12 PM PST 23
Peak memory 207108 kb
Host smart-dc54bf55-4e81-4c6a-a90f-3d2518a15505
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239199252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.3239199252
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.3119805804
Short name T695
Test name
Test status
Simulation time 160696122997 ps
CPU time 658.93 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:57:18 PM PST 23
Peak memory 239892 kb
Host smart-e56876ff-821a-4065-902a-fc888a7af14e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3119805804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.3119805804
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.625238951
Short name T127
Test name
Test status
Simulation time 415330047122 ps
CPU time 1839.4 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 02:16:55 PM PST 23
Peak memory 247460 kb
Host smart-320de15b-5ad8-4baf-9ed4-24bad2ee98ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625238951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.625238951
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.323416705
Short name T538
Test name
Test status
Simulation time 14895734 ps
CPU time 0.58 seconds
Started Dec 24 01:45:43 PM PST 23
Finished Dec 24 01:45:44 PM PST 23
Peak memory 193116 kb
Host smart-05e988be-a931-47c0-88d1-bc6ac81ddcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323416705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.323416705
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4256887236
Short name T3
Test name
Test status
Simulation time 460885102 ps
CPU time 14.59 seconds
Started Dec 24 01:45:11 PM PST 23
Finished Dec 24 01:45:30 PM PST 23
Peak memory 206888 kb
Host smart-6df1b472-c062-4322-95a4-5b3c3aa275d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256887236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4256887236
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2643013903
Short name T312
Test name
Test status
Simulation time 1534791691 ps
CPU time 17.05 seconds
Started Dec 24 01:44:58 PM PST 23
Finished Dec 24 01:45:16 PM PST 23
Peak memory 198604 kb
Host smart-86f99dde-b7f0-4fa9-bbc4-b9b333229803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643013903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2643013903
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1507066007
Short name T208
Test name
Test status
Simulation time 641115283 ps
CPU time 7.73 seconds
Started Dec 24 01:44:58 PM PST 23
Finished Dec 24 01:45:07 PM PST 23
Peak memory 198588 kb
Host smart-6efe6f78-a18a-4f37-a261-e3e1e8d31ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507066007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1507066007
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1431299573
Short name T118
Test name
Test status
Simulation time 12005377479 ps
CPU time 139.77 seconds
Started Dec 24 01:45:34 PM PST 23
Finished Dec 24 01:47:54 PM PST 23
Peak memory 198876 kb
Host smart-9b042878-42d2-42c5-a3bf-10e7421f405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431299573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1431299573
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.422112772
Short name T756
Test name
Test status
Simulation time 1655365348 ps
CPU time 86.26 seconds
Started Dec 24 01:45:15 PM PST 23
Finished Dec 24 01:46:48 PM PST 23
Peak memory 198748 kb
Host smart-4afe3d5f-cc2d-4b46-b6ff-4ae2d1b3f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422112772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.422112772
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.4052608893
Short name T270
Test name
Test status
Simulation time 922996758 ps
CPU time 3.16 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:19 PM PST 23
Peak memory 198500 kb
Host smart-91ed0d9a-1c6a-4746-8c72-871daff0ab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052608893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.4052608893
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3857171480
Short name T715
Test name
Test status
Simulation time 238555427045 ps
CPU time 875.43 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:59:54 PM PST 23
Peak memory 245876 kb
Host smart-b1b17885-25df-4f08-9afd-fab364c67b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857171480 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3857171480
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3510005637
Short name T298
Test name
Test status
Simulation time 22545494870 ps
CPU time 380.88 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:51:38 PM PST 23
Peak memory 214264 kb
Host smart-c0667051-8b07-4b9a-b4bd-7e91c296674d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3510005637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3510005637
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1899698197
Short name T504
Test name
Test status
Simulation time 86103500 ps
CPU time 0.88 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:45:10 PM PST 23
Peak memory 196596 kb
Host smart-5eef6c19-be83-4d2b-bd8a-48d404ff7ed8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899698197 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1899698197
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3067978389
Short name T276
Test name
Test status
Simulation time 15326317709 ps
CPU time 403.65 seconds
Started Dec 24 01:45:08 PM PST 23
Finished Dec 24 01:51:53 PM PST 23
Peak memory 198848 kb
Host smart-1c7dc614-77ac-4667-b96f-f87022817b45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067978389 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.3067978389
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1772640634
Short name T280
Test name
Test status
Simulation time 11150068223 ps
CPU time 32.32 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:52 PM PST 23
Peak memory 198876 kb
Host smart-2b4c181f-0226-47b4-891e-00b3e244df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772640634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1772640634
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.3311497957
Short name T114
Test name
Test status
Simulation time 26556789041 ps
CPU time 345.21 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:52:00 PM PST 23
Peak memory 206984 kb
Host smart-5caf21b3-05ca-45b2-bd75-139778c8456a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3311497957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.3311497957
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.3029093235
Short name T425
Test name
Test status
Simulation time 313265839761 ps
CPU time 594.49 seconds
Started Dec 24 01:46:06 PM PST 23
Finished Dec 24 01:56:03 PM PST 23
Peak memory 247816 kb
Host smart-433df6ad-0964-49f7-bed9-9f8028be12a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3029093235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.3029093235
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.1704382691
Short name T320
Test name
Test status
Simulation time 140496648368 ps
CPU time 1478.36 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 02:11:02 PM PST 23
Peak memory 215200 kb
Host smart-ba8be86f-346a-4e0a-a759-7b7f1b325528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704382691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.1704382691
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.3109639604
Short name T590
Test name
Test status
Simulation time 21355669148 ps
CPU time 364.48 seconds
Started Dec 24 01:46:18 PM PST 23
Finished Dec 24 01:52:24 PM PST 23
Peak memory 206928 kb
Host smart-f9863234-d38d-400c-9343-f9133d777916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109639604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.3109639604
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.4235201354
Short name T555
Test name
Test status
Simulation time 389514881211 ps
CPU time 1207.16 seconds
Started Dec 24 01:46:17 PM PST 23
Finished Dec 24 02:06:25 PM PST 23
Peak memory 256112 kb
Host smart-553b61b7-6343-48f0-94a4-799b0644a0ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4235201354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.4235201354
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.756004706
Short name T633
Test name
Test status
Simulation time 92404898340 ps
CPU time 363.72 seconds
Started Dec 24 01:46:49 PM PST 23
Finished Dec 24 01:53:01 PM PST 23
Peak memory 215288 kb
Host smart-b98d915f-6906-4412-a9a8-9bdbff1f2c99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=756004706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.756004706
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.3892561462
Short name T536
Test name
Test status
Simulation time 44487017427 ps
CPU time 872.39 seconds
Started Dec 24 01:46:49 PM PST 23
Finished Dec 24 02:01:30 PM PST 23
Peak memory 230976 kb
Host smart-191d95b4-251e-42f7-815f-e777af9e7cfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3892561462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.3892561462
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.4152076920
Short name T478
Test name
Test status
Simulation time 55784253980 ps
CPU time 1610.14 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 02:13:43 PM PST 23
Peak memory 247712 kb
Host smart-21b05864-ec86-4dbf-a96b-3fbffc4e6dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4152076920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.4152076920
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.2936720214
Short name T362
Test name
Test status
Simulation time 118439016960 ps
CPU time 1583.38 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 02:13:14 PM PST 23
Peak memory 246572 kb
Host smart-4494f4dd-fd6e-474d-a994-fd099fe375dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936720214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.2936720214
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.252988045
Short name T313
Test name
Test status
Simulation time 161928865689 ps
CPU time 615.54 seconds
Started Dec 24 01:46:14 PM PST 23
Finished Dec 24 01:56:31 PM PST 23
Peak memory 247952 kb
Host smart-35cab960-eea3-41be-b55b-7b5dc04071ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=252988045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.252988045
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.853652142
Short name T364
Test name
Test status
Simulation time 11805896 ps
CPU time 0.56 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:45:21 PM PST 23
Peak memory 193092 kb
Host smart-4702f0aa-0898-4026-a949-9b91da949f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853652142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.853652142
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3958416606
Short name T129
Test name
Test status
Simulation time 3277270441 ps
CPU time 54.37 seconds
Started Dec 24 01:45:35 PM PST 23
Finished Dec 24 01:46:31 PM PST 23
Peak memory 231608 kb
Host smart-2ad55c1b-64e3-4689-bba6-acc7978ac032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3958416606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3958416606
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.456920371
Short name T50
Test name
Test status
Simulation time 3166485916 ps
CPU time 22.07 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:45 PM PST 23
Peak memory 198792 kb
Host smart-c42a6b86-a7bd-4199-a9b1-24054a7b6d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456920371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.456920371
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2840125169
Short name T691
Test name
Test status
Simulation time 1949996722 ps
CPU time 103.61 seconds
Started Dec 24 01:45:21 PM PST 23
Finished Dec 24 01:47:11 PM PST 23
Peak memory 198700 kb
Host smart-2ef81e00-919f-48f1-a023-55c7bace790f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840125169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2840125169
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.78428528
Short name T476
Test name
Test status
Simulation time 1962425614 ps
CPU time 25.23 seconds
Started Dec 24 01:45:42 PM PST 23
Finished Dec 24 01:46:08 PM PST 23
Peak memory 198704 kb
Host smart-a960a562-13c7-4319-b7e4-1a36ed54873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78428528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.78428528
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1507608691
Short name T360
Test name
Test status
Simulation time 1163220082 ps
CPU time 62.06 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:46:25 PM PST 23
Peak memory 198736 kb
Host smart-6728f4f8-eab1-4b20-b9d6-cff537cb4334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507608691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1507608691
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1192354929
Short name T437
Test name
Test status
Simulation time 519263876 ps
CPU time 1.73 seconds
Started Dec 24 01:45:12 PM PST 23
Finished Dec 24 01:45:20 PM PST 23
Peak memory 198400 kb
Host smart-8dd246de-90e9-483f-b9d9-178296e35256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192354929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1192354929
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.440711623
Short name T740
Test name
Test status
Simulation time 92496944562 ps
CPU time 424.12 seconds
Started Dec 24 01:45:14 PM PST 23
Finished Dec 24 01:52:24 PM PST 23
Peak memory 239732 kb
Host smart-8724b95c-9b9e-4b4d-a1b9-0489bece847a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440711623 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.440711623
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1559363024
Short name T392
Test name
Test status
Simulation time 157559440338 ps
CPU time 2838.77 seconds
Started Dec 24 01:45:35 PM PST 23
Finished Dec 24 02:32:54 PM PST 23
Peak memory 246496 kb
Host smart-e297cb5c-9d7c-4d08-a32b-ddd724b60886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559363024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1559363024
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.91294917
Short name T818
Test name
Test status
Simulation time 90851824 ps
CPU time 0.89 seconds
Started Dec 24 01:45:36 PM PST 23
Finished Dec 24 01:45:38 PM PST 23
Peak memory 195520 kb
Host smart-d61a47b3-dedd-46e0-a9c9-262c6fce2e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91294917 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_hmac_vectors.91294917
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.998612469
Short name T32
Test name
Test status
Simulation time 14532798651 ps
CPU time 359.15 seconds
Started Dec 24 01:45:36 PM PST 23
Finished Dec 24 01:51:36 PM PST 23
Peak memory 198892 kb
Host smart-d8aaa698-342b-4129-ab97-ac53a5f85ccb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998612469 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.hmac_test_sha_vectors.998612469
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.301594433
Short name T716
Test name
Test status
Simulation time 1333539662 ps
CPU time 39.31 seconds
Started Dec 24 01:45:39 PM PST 23
Finished Dec 24 01:46:20 PM PST 23
Peak memory 198732 kb
Host smart-bbc8426f-9076-41b3-95ae-e5c950b89cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301594433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.301594433
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.3204282219
Short name T562
Test name
Test status
Simulation time 42417351649 ps
CPU time 2032.4 seconds
Started Dec 24 01:46:13 PM PST 23
Finished Dec 24 02:20:07 PM PST 23
Peak memory 233880 kb
Host smart-421fe9e2-efa4-4ca6-ae83-474c7d08dfe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3204282219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.3204282219
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.4234955415
Short name T607
Test name
Test status
Simulation time 11835933043 ps
CPU time 596.39 seconds
Started Dec 24 01:46:39 PM PST 23
Finished Dec 24 01:56:45 PM PST 23
Peak memory 215104 kb
Host smart-29cd2452-df83-45f4-a492-5905b066526c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234955415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.4234955415
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.1625167218
Short name T384
Test name
Test status
Simulation time 37962333981 ps
CPU time 185.73 seconds
Started Dec 24 01:46:44 PM PST 23
Finished Dec 24 01:49:58 PM PST 23
Peak memory 198840 kb
Host smart-c5a77156-bd54-4b24-9426-513c64671c5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625167218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.1625167218
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3166730301
Short name T125
Test name
Test status
Simulation time 55544743485 ps
CPU time 2510.53 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 02:28:15 PM PST 23
Peak memory 257184 kb
Host smart-63368f42-2666-44da-8dc9-3cea6ed6821d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166730301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.3166730301
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.3875096565
Short name T658
Test name
Test status
Simulation time 96353477125 ps
CPU time 772.56 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:59:45 PM PST 23
Peak memory 235784 kb
Host smart-9ea8763e-d832-4d4f-89f7-3aac51ede02a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875096565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.3875096565
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.2078730665
Short name T112
Test name
Test status
Simulation time 22019025755 ps
CPU time 395.53 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 01:53:28 PM PST 23
Peak memory 207080 kb
Host smart-97491a79-a59e-4b3b-9831-a991053c6fc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078730665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.2078730665
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1885105340
Short name T628
Test name
Test status
Simulation time 147297407661 ps
CPU time 996.38 seconds
Started Dec 24 01:46:43 PM PST 23
Finished Dec 24 02:03:29 PM PST 23
Peak memory 231564 kb
Host smart-72ae4c38-6b05-4e0d-8192-2990a74438ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1885105340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.1885105340
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.863051654
Short name T511
Test name
Test status
Simulation time 167683758224 ps
CPU time 623.03 seconds
Started Dec 24 01:46:36 PM PST 23
Finished Dec 24 01:57:04 PM PST 23
Peak memory 231264 kb
Host smart-0fcf9dcc-18c2-4fe5-881c-2b0feb0a6125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=863051654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.863051654
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.176059137
Short name T5
Test name
Test status
Simulation time 28734217967 ps
CPU time 526.46 seconds
Started Dec 24 01:46:38 PM PST 23
Finished Dec 24 01:55:34 PM PST 23
Peak memory 247796 kb
Host smart-d29b1ccc-6107-4326-946d-4ed6a04a0884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176059137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.176059137
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.194096185
Short name T804
Test name
Test status
Simulation time 26947264 ps
CPU time 0.55 seconds
Started Dec 24 01:46:34 PM PST 23
Finished Dec 24 01:46:39 PM PST 23
Peak memory 193116 kb
Host smart-315a80c6-f62b-4b85-858e-9ba92024a7e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194096185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.194096185
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.650793168
Short name T340
Test name
Test status
Simulation time 485178501 ps
CPU time 17.75 seconds
Started Dec 24 01:45:41 PM PST 23
Finished Dec 24 01:46:00 PM PST 23
Peak memory 226160 kb
Host smart-deafaa71-a64c-4802-9938-b044ff10aa3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650793168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.650793168
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1943695035
Short name T139
Test name
Test status
Simulation time 3322625538 ps
CPU time 58.75 seconds
Started Dec 24 01:45:17 PM PST 23
Finished Dec 24 01:46:22 PM PST 23
Peak memory 198720 kb
Host smart-024703bc-d786-45f8-a683-b59bc9237a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943695035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1943695035
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1835628413
Short name T335
Test name
Test status
Simulation time 2404231569 ps
CPU time 93.7 seconds
Started Dec 24 01:45:45 PM PST 23
Finished Dec 24 01:47:19 PM PST 23
Peak memory 198816 kb
Host smart-da7257c8-8bfd-4311-9e89-39ddbaa87ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835628413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1835628413
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3971075353
Short name T718
Test name
Test status
Simulation time 10993259995 ps
CPU time 91.89 seconds
Started Dec 24 01:45:57 PM PST 23
Finished Dec 24 01:47:30 PM PST 23
Peak memory 198856 kb
Host smart-2801a638-04b4-44d2-8b29-a7213f1a1ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971075353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3971075353
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3803687865
Short name T387
Test name
Test status
Simulation time 2098681527 ps
CPU time 27.44 seconds
Started Dec 24 01:45:16 PM PST 23
Finished Dec 24 01:45:51 PM PST 23
Peak memory 198444 kb
Host smart-be272f41-f9be-44bf-a45d-d53094a75796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803687865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3803687865
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1468090480
Short name T563
Test name
Test status
Simulation time 157850191 ps
CPU time 2.32 seconds
Started Dec 24 01:45:38 PM PST 23
Finished Dec 24 01:45:41 PM PST 23
Peak memory 198644 kb
Host smart-496a113c-658f-494f-956d-fcf08eee1eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468090480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1468090480
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2640609686
Short name T428
Test name
Test status
Simulation time 457498302480 ps
CPU time 1357.75 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 02:08:43 PM PST 23
Peak memory 240212 kb
Host smart-847f103f-e30c-4183-a561-64113c7cb4a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640609686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2640609686
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1512911883
Short name T546
Test name
Test status
Simulation time 296978725639 ps
CPU time 2209.06 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 02:22:56 PM PST 23
Peak memory 262988 kb
Host smart-0550d6aa-efd9-4d73-859f-66e031d175fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1512911883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1512911883
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2432060599
Short name T395
Test name
Test status
Simulation time 134499865 ps
CPU time 1.13 seconds
Started Dec 24 01:46:02 PM PST 23
Finished Dec 24 01:46:07 PM PST 23
Peak memory 196944 kb
Host smart-56dc68cb-4137-470a-81dd-23ff171a7a86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432060599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2432060599
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.521161367
Short name T429
Test name
Test status
Simulation time 15711935784 ps
CPU time 385.65 seconds
Started Dec 24 01:45:54 PM PST 23
Finished Dec 24 01:52:21 PM PST 23
Peak memory 198844 kb
Host smart-565bee0b-e580-46f6-b737-75bbdcfe02aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521161367 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.521161367
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3583687032
Short name T229
Test name
Test status
Simulation time 6930782998 ps
CPU time 45.8 seconds
Started Dec 24 01:46:00 PM PST 23
Finished Dec 24 01:46:51 PM PST 23
Peak memory 198764 kb
Host smart-5608b8dc-1777-4c2f-8bfe-8ed3918975a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583687032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3583687032
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.1899898683
Short name T637
Test name
Test status
Simulation time 92517946124 ps
CPU time 910.78 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 02:01:32 PM PST 23
Peak memory 215228 kb
Host smart-1b17bd0b-dec9-4af1-8c7c-5c61d358413a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899898683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.1899898683
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.3633333515
Short name T424
Test name
Test status
Simulation time 178932964321 ps
CPU time 656.96 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 01:57:47 PM PST 23
Peak memory 247812 kb
Host smart-a799d888-7fbb-4100-9b3f-5b017aec113c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3633333515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.3633333515
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.1426606892
Short name T728
Test name
Test status
Simulation time 703223494549 ps
CPU time 2225.18 seconds
Started Dec 24 01:46:21 PM PST 23
Finished Dec 24 02:23:29 PM PST 23
Peak memory 239924 kb
Host smart-da8a96cb-f35e-4d77-a17a-b20d2260e4f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1426606892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.1426606892
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.556170324
Short name T264
Test name
Test status
Simulation time 200308728759 ps
CPU time 908.06 seconds
Started Dec 24 01:46:41 PM PST 23
Finished Dec 24 02:01:59 PM PST 23
Peak memory 210320 kb
Host smart-70513d5b-ed9f-4196-b514-a7123af175af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556170324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.556170324
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2513394610
Short name T292
Test name
Test status
Simulation time 30263532093 ps
CPU time 239.27 seconds
Started Dec 24 01:46:17 PM PST 23
Finished Dec 24 01:50:18 PM PST 23
Peak memory 214448 kb
Host smart-d8572aed-8077-4830-b523-f375632a297c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513394610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.2513394610
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3254554893
Short name T135
Test name
Test status
Simulation time 502829494259 ps
CPU time 2276.29 seconds
Started Dec 24 01:46:40 PM PST 23
Finished Dec 24 02:24:46 PM PST 23
Peak memory 224940 kb
Host smart-b01960f6-2316-494c-b04e-179ae79b2cb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254554893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3254554893
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.703091219
Short name T573
Test name
Test status
Simulation time 188680455645 ps
CPU time 2854.45 seconds
Started Dec 24 01:46:46 PM PST 23
Finished Dec 24 02:34:28 PM PST 23
Peak memory 248128 kb
Host smart-30a3afa2-0345-4bb9-b204-cfae5e937516
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=703091219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.703091219
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1096118445
Short name T348
Test name
Test status
Simulation time 58576196707 ps
CPU time 1095.43 seconds
Started Dec 24 01:46:49 PM PST 23
Finished Dec 24 02:05:13 PM PST 23
Peak memory 235488 kb
Host smart-09e363a3-9819-4241-855e-bb21b3c30250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096118445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1096118445
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.3084144009
Short name T124
Test name
Test status
Simulation time 45172138786 ps
CPU time 2104.66 seconds
Started Dec 24 01:46:42 PM PST 23
Finished Dec 24 02:21:57 PM PST 23
Peak memory 256216 kb
Host smart-6330374f-a7c2-4fd7-af83-3e8eba0c4371
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084144009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.3084144009
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.1689968788
Short name T106
Test name
Test status
Simulation time 79211363376 ps
CPU time 3092.04 seconds
Started Dec 24 01:46:19 PM PST 23
Finished Dec 24 02:37:53 PM PST 23
Peak memory 260936 kb
Host smart-da143d40-6927-4fb7-9e7e-f4f4bd06dbd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689968788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.1689968788
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
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