Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	40011700	1			T13	11		T16	11		T18	5
all_values[1]	40011700	1			T13	11		T16	11		T18	5
all_values[2]	40011700	1			T13	11		T16	11		T18	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150753

1

T13

22

T16

20

T18

11

auto[1]

119884347

1

T13

11

T16

13

T18

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87608335

1

T13

20

T16

18

T18

12

auto[1]

32426765

1

T13

13

T16

15

T18

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	49747	1			T13	4		T16	6		T18	5
all_values[0]	auto[0]	auto[1]	1341	1			T13	3		T16	1		T20	4
all_values[0]	auto[1]	auto[0]	39793301	1			T13	2		T16	2		T20	1
all_values[0]	auto[1]	auto[1]	167311	1			T13	2		T16	2		T20	3
all_values[1]	auto[0]	auto[0]	27458	1			T13	6		T16	3		T18	3
all_values[1]	auto[0]	auto[1]	25299	1			T13	1		T16	1		T18	2
all_values[1]	auto[1]	auto[0]	22650746	1			T13	1		T16	3		T23	2
all_values[1]	auto[1]	auto[1]	17308197	1			T13	3		T16	4		T20	1
all_values[2]	auto[0]	auto[0]	34029	1			T13	6		T16	3		T18	1
all_values[2]	auto[0]	auto[1]	12879	1			T13	2		T16	6		T23	3
all_values[2]	auto[1]	auto[0]	25053054	1			T13	1		T16	1		T18	3
all_values[2]	auto[1]	auto[1]	14911738	1			T13	2		T16	1		T18	1