Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19837206

1

T1

14176

T2

1500

T3

8882

auto[1]

9705438

1

T1

4094

T2

2162

T3

9118

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9872837

1

T1

9701

T2

1996

T3

9572

auto[1]

19669807

1

T1

8569

T2

1666

T3

8428

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16849079

1

T2

520

T3

9350

T7

17875

auto[1]

12693565

1

T1

18270

T2

3142

T3

8650

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	16450377	1			T1	6393		T2	1963		T3	142
fifo_depth[1]	1532036	1			T1	1337		T2	213		T3	167
fifo_depth[2]	1399248	1			T1	1303		T2	173		T3	377
fifo_depth[3]	1199527	1			T1	1354		T2	189		T3	383
fifo_depth[4]	1161267	1			T1	1305		T2	179		T3	817
fifo_depth[5]	1003177	1			T1	1384		T2	188		T3	437
fifo_depth[6]	1024147	1			T1	1298		T2	188		T3	1089
fifo_depth[7]	877228	1			T1	1153		T2	176		T3	700
fifo_depth[8]	996408	1			T1	1017		T2	144		T3	1622
fifo_depth[9]	598497	1			T1	698		T2	97		T3	937
fifo_depth[10]	583819	1			T1	498		T2	70		T3	1531
fifo_depth[11]	350616	1			T1	295		T2	41		T3	992
fifo_depth[12]	564427	1			T1	134		T2	20		T3	2044
fifo_depth[13]	247467	1			T1	62		T2	14		T3	1165
fifo_depth[14]	405983	1			T1	29		T2	5		T3	1908
fifo_depth[15]	223181	1			T1	10		T3	1085		T8	1
fifo_depth[16]	925239	1			T2	2		T3	2604		T8	4

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13092267

1

T1

11877

T2

1699

T3

17858

auto[1]

16450377

1

T1

6393

T2

1963

T3

142

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28617405

1

T1

18270

T2

3660

T3

15396

auto[1]

925239

1

T2

2

T3

2604

T8

4

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

998247

1

T3

421

T7

400

T4

190

auto[0]

auto[0]

auto[0]

auto[1]

949468

1

T3

3478

T7

532

T4

2

auto[0]

auto[0]

auto[1]

auto[0]

3490967

1

T2

146

T3

1909

T7

232

auto[0]

auto[0]

auto[1]

auto[1]

948667

1

T3

3427

T7

435

T4

21

auto[0]

auto[1]

auto[0]

auto[0]

1689977

1

T1

4716

T3

3502

T7

1112

auto[0]

auto[1]

auto[0]

auto[1]

1659755

1

T1

1569

T2

1127

T3

2101

auto[0]

auto[1]

auto[1]

auto[0]

1754225

1

T1

4488

T2

127

T3

3020

auto[0]

auto[1]

auto[1]

auto[1]

1600961

1

T1

1104

T2

299

T7

808

auto[1]

auto[0]

auto[0]

auto[0]

815425

1

T2

275

T3

4

T7

4003

auto[1]

auto[0]

auto[0]

auto[1]

773861

1

T3

41

T7

5124

T4

46

auto[1]

auto[0]

auto[1]

auto[0]

8054260

1

T2

98

T3

15

T7

2009

auto[1]

auto[0]

auto[1]

auto[1]

818184

1

T2

1

T3

55

T7

5140

auto[1]

auto[1]

auto[0]

auto[0]

1501722

1

T1

2603

T2

1

T3

9

auto[1]

auto[1]

auto[0]

auto[1]

1484382

1

T1

813

T2

593

T3

16

auto[1]

auto[1]

auto[1]

auto[0]

1532383

1

T1

2369

T2

853

T3

2

auto[1]

auto[1]

auto[1]

auto[1]

1470160

1

T1

608

T2

142

T7

8653

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1698584

1

T2

275

T3

386

T7

4403

auto[0]

auto[0]

auto[0]

auto[1]

1616649

1

T3

3144

T7

5656

T4

48

auto[0]

auto[0]

auto[1]

auto[0]

11436563

1

T2

244

T3

1410

T7

2241

auto[0]

auto[0]

auto[1]

auto[1]

1644618

1

T2

1

T3

2464

T7

5575

auto[0]

auto[1]

auto[0]

auto[0]

3073060

1

T1

7319

T2

1

T3

3254

auto[0]

auto[1]

auto[0]

auto[1]

3031304

1

T1

2382

T2

1719

T3

1989

auto[0]

auto[1]

auto[1]

auto[0]

3161343

1

T1

6857

T2

980

T3

2749

auto[0]

auto[1]

auto[1]

auto[1]

2955284

1

T1

1712

T2

440

T7

9461

auto[1]

auto[0]

auto[0]

auto[0]

115088

1

T3

39

T5

897

T39

3083

auto[1]

auto[0]

auto[0]

auto[1]

106680

1

T3

375

T8

1

T5

670

auto[1]

auto[0]

auto[1]

auto[0]

108664

1

T3

514

T8

1

T5

792

auto[1]

auto[0]

auto[1]

auto[1]

122233

1

T3

1018

T8

1

T5

282

auto[1]

auto[1]

auto[0]

auto[0]

118639

1

T3

257

T8

1

T5

1590

auto[1]

auto[1]

auto[0]

auto[1]

112833

1

T2

1

T3

128

T5

371

auto[1]

auto[1]

auto[1]

auto[0]

125265

1

T3

273

T5

4439

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

115837

1

T2

1

T5

1208

T39

3296

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	815425	1			T2	275		T3	4		T7	4003
fifo_depth[0]	auto[0]	auto[0]	auto[1]	773861	1			T3	41		T7	5124		T4	46
fifo_depth[0]	auto[0]	auto[1]	auto[0]	8054260	1			T2	98		T3	15		T7	2009
fifo_depth[0]	auto[0]	auto[1]	auto[1]	818184	1			T2	1		T3	55		T7	5140
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1501722	1			T1	2603		T2	1		T3	9
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1484382	1			T1	813		T2	593		T3	16
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1532383	1			T1	2369		T2	853		T3	2
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1470160	1			T1	608		T2	142		T7	8653
fifo_depth[1]	auto[0]	auto[0]	auto[0]	78986	1			T3	1		T7	159		T4	7
fifo_depth[1]	auto[0]	auto[0]	auto[1]	74005	1			T3	47		T7	233		T5	191
fifo_depth[1]	auto[0]	auto[1]	auto[0]	620506	1			T2	19		T3	3		T7	100
fifo_depth[1]	auto[0]	auto[1]	auto[1]	74377	1			T3	43		T7	221		T4	2
fifo_depth[1]	auto[1]	auto[0]	auto[0]	173563	1			T1	543		T3	37		T7	650
fifo_depth[1]	auto[1]	auto[0]	auto[1]	168648	1			T1	176		T2	134		T3	25
fifo_depth[1]	auto[1]	auto[1]	auto[0]	175392	1			T1	498		T2	14		T3	11
fifo_depth[1]	auto[1]	auto[1]	auto[1]	166559	1			T1	120		T2	46		T7	432
fifo_depth[2]	auto[0]	auto[0]	auto[0]	75570	1			T3	5		T7	117		T4	119
fifo_depth[2]	auto[0]	auto[0]	auto[1]	71404	1			T3	109		T7	211		T5	161
fifo_depth[2]	auto[0]	auto[1]	auto[0]	548992	1			T2	15		T3	9		T7	56
fifo_depth[2]	auto[0]	auto[1]	auto[1]	70246	1			T3	187		T7	123		T4	1
fifo_depth[2]	auto[1]	auto[0]	auto[0]	160314	1			T1	540		T3	26		T7	316
fifo_depth[2]	auto[1]	auto[0]	auto[1]	156017	1			T1	174		T2	123		T3	29
fifo_depth[2]	auto[1]	auto[1]	auto[0]	163672	1			T1	475		T2	14		T3	12
fifo_depth[2]	auto[1]	auto[1]	auto[1]	153033	1			T1	114		T2	21		T7	235
fifo_depth[3]	auto[0]	auto[0]	auto[0]	66765	1			T7	33		T4	7		T5	160
fifo_depth[3]	auto[0]	auto[0]	auto[1]	63083	1			T3	108		T7	42		T4	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	444234	1			T2	21		T3	5		T7	33
fifo_depth[3]	auto[0]	auto[1]	auto[1]	61381	1			T3	181		T7	38		T4	1
fifo_depth[3]	auto[1]	auto[0]	auto[0]	143541	1			T1	528		T3	45		T7	81
fifo_depth[3]	auto[1]	auto[0]	auto[1]	139764	1			T1	187		T2	116		T3	25
fifo_depth[3]	auto[1]	auto[1]	auto[0]	145595	1			T1	523		T2	16		T3	19
fifo_depth[3]	auto[1]	auto[1]	auto[1]	135164	1			T1	116		T2	36		T7	72
fifo_depth[4]	auto[0]	auto[0]	auto[0]	75903	1			T3	4		T7	72		T4	54
fifo_depth[4]	auto[0]	auto[0]	auto[1]	72896	1			T3	216		T7	33		T4	1
fifo_depth[4]	auto[0]	auto[1]	auto[0]	354356	1			T2	13		T3	42		T7	21
fifo_depth[4]	auto[0]	auto[1]	auto[1]	71231	1			T3	189		T7	36		T4	17
fifo_depth[4]	auto[1]	auto[0]	auto[0]	149409	1			T1	552		T3	153		T7	45
fifo_depth[4]	auto[1]	auto[0]	auto[1]	144614	1			T1	178		T2	123		T3	185
fifo_depth[4]	auto[1]	auto[1]	auto[0]	152035	1			T1	462		T2	8		T3	28
fifo_depth[4]	auto[1]	auto[1]	auto[1]	140823	1			T1	113		T2	35		T7	41
fifo_depth[5]	auto[0]	auto[0]	auto[0]	64437	1			T3	10		T7	12		T5	175
fifo_depth[5]	auto[0]	auto[0]	auto[1]	60605	1			T3	94		T7	11		T5	225
fifo_depth[5]	auto[0]	auto[1]	auto[0]	293536	1			T2	20		T3	35		T7	12
fifo_depth[5]	auto[0]	auto[1]	auto[1]	58172	1			T3	176		T7	12		T5	170
fifo_depth[5]	auto[1]	auto[0]	auto[0]	134313	1			T1	556		T3	58		T7	12
fifo_depth[5]	auto[1]	auto[0]	auto[1]	130278	1			T1	173		T2	125		T3	42
fifo_depth[5]	auto[1]	auto[1]	auto[0]	136040	1			T1	520		T2	14		T3	22
fifo_depth[5]	auto[1]	auto[1]	auto[1]	125796	1			T1	135		T2	29		T7	15
fifo_depth[6]	auto[0]	auto[0]	auto[0]	70658	1			T3	11		T7	5		T4	3
fifo_depth[6]	auto[0]	auto[0]	auto[1]	68239	1			T3	201		T7	2		T5	626
fifo_depth[6]	auto[0]	auto[1]	auto[0]	267207	1			T2	13		T3	119		T7	7
fifo_depth[6]	auto[0]	auto[1]	auto[1]	66096	1			T3	187		T7	5		T5	201
fifo_depth[6]	auto[1]	auto[0]	auto[0]	139091	1			T1	504		T3	220		T7	6
fifo_depth[6]	auto[1]	auto[0]	auto[1]	136825	1			T1	177		T2	135		T3	271
fifo_depth[6]	auto[1]	auto[1]	auto[0]	144812	1			T1	477		T2	13		T3	80
fifo_depth[6]	auto[1]	auto[1]	auto[1]	131219	1			T1	140		T2	27		T7	13
fifo_depth[7]	auto[0]	auto[0]	auto[0]	62159	1			T3	10		T8	2		T5	185
fifo_depth[7]	auto[0]	auto[0]	auto[1]	58121	1			T3	87		T8	1		T5	533
fifo_depth[7]	auto[0]	auto[1]	auto[0]	213891	1			T2	14		T3	100		T7	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	55526	1			T3	168		T5	201		T10	151
fifo_depth[7]	auto[1]	auto[0]	auto[0]	123324	1			T1	442		T3	122		T7	1
fifo_depth[7]	auto[1]	auto[0]	auto[1]	121989	1			T1	151		T2	111		T3	132
fifo_depth[7]	auto[1]	auto[1]	auto[0]	126377	1			T1	448		T2	14		T3	81
fifo_depth[7]	auto[1]	auto[1]	auto[1]	115841	1			T1	112		T2	37		T4	6
fifo_depth[8]	auto[0]	auto[0]	auto[0]	84150	1			T3	105		T7	2		T5	181
fifo_depth[8]	auto[0]	auto[0]	auto[1]	78363	1			T3	182		T5	902		T10	112
fifo_depth[8]	auto[0]	auto[1]	auto[0]	193346	1			T2	14		T3	270		T8	1
fifo_depth[8]	auto[0]	auto[1]	auto[1]	82170	1			T3	231		T5	634		T10	129
fifo_depth[8]	auto[1]	auto[0]	auto[0]	142731	1			T1	423		T3	211		T4	5
fifo_depth[8]	auto[1]	auto[0]	auto[1]	139638	1			T1	126		T2	93		T3	243
fifo_depth[8]	auto[1]	auto[1]	auto[0]	143177	1			T1	385		T2	16		T3	380
fifo_depth[8]	auto[1]	auto[1]	auto[1]	132833	1			T1	83		T2	21		T4	8
fifo_depth[9]	auto[0]	auto[0]	auto[0]	47190	1			T3	9		T5	112		T10	65
fifo_depth[9]	auto[0]	auto[0]	auto[1]	44738	1			T3	90		T8	1		T5	713
fifo_depth[9]	auto[0]	auto[1]	auto[0]	118918	1			T2	8		T3	64		T7	1
fifo_depth[9]	auto[0]	auto[1]	auto[1]	41628	1			T3	161		T5	160		T10	96
fifo_depth[9]	auto[1]	auto[0]	auto[0]	87414	1			T1	281		T3	140		T7	1
fifo_depth[9]	auto[1]	auto[0]	auto[1]	86426	1			T1	95		T2	62		T3	118
fifo_depth[9]	auto[1]	auto[1]	auto[0]	91048	1			T1	262		T2	10		T3	355
fifo_depth[9]	auto[1]	auto[1]	auto[1]	81135	1			T1	60		T2	17		T4	1
fifo_depth[10]	auto[0]	auto[0]	auto[0]	55000	1			T3	76		T5	85		T10	38
fifo_depth[10]	auto[0]	auto[0]	auto[1]	52674	1			T3	239		T8	2		T5	706
fifo_depth[10]	auto[0]	auto[1]	auto[0]	97545	1			T2	6		T3	175		T8	2
fifo_depth[10]	auto[0]	auto[1]	auto[1]	48089	1			T3	174		T8	1		T5	426
fifo_depth[10]	auto[1]	auto[0]	auto[0]	80696	1			T1	169		T3	354		T8	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	83474	1			T1	55		T2	43		T3	249
fifo_depth[10]	auto[1]	auto[1]	auto[0]	90070	1			T1	221		T2	3		T3	264
fifo_depth[10]	auto[1]	auto[1]	auto[1]	76271	1			T1	53		T2	18		T4	2
fifo_depth[11]	auto[0]	auto[0]	auto[0]	34284	1			T3	7		T5	82		T10	23
fifo_depth[11]	auto[0]	auto[0]	auto[1]	32752	1			T3	123		T8	2		T5	585
fifo_depth[11]	auto[0]	auto[1]	auto[0]	56861	1			T2	3		T3	73		T8	1
fifo_depth[11]	auto[0]	auto[1]	auto[1]	29519	1			T3	141		T8	1		T5	111
fifo_depth[11]	auto[1]	auto[0]	auto[0]	48723	1			T1	104		T3	269		T8	3
fifo_depth[11]	auto[1]	auto[0]	auto[1]	49540	1			T1	44		T2	30		T3	112
fifo_depth[11]	auto[1]	auto[1]	auto[0]	53813	1			T1	113		T2	3		T3	267
fifo_depth[11]	auto[1]	auto[1]	auto[1]	45124	1			T1	34		T2	5		T4	2
fifo_depth[12]	auto[0]	auto[0]	auto[0]	62201	1			T3	72		T8	1		T5	158
fifo_depth[12]	auto[0]	auto[0]	auto[1]	60583	1			T3	651		T5	773		T10	13
fifo_depth[12]	auto[0]	auto[1]	auto[0]	70624	1			T3	228		T5	504		T10	7
fifo_depth[12]	auto[0]	auto[1]	auto[1]	65507	1			T3	166		T5	332		T10	11
fifo_depth[12]	auto[1]	auto[0]	auto[0]	75721	1			T1	47		T3	487		T8	4
fifo_depth[12]	auto[1]	auto[0]	auto[1]	76269	1			T1	16		T2	16		T3	189
fifo_depth[12]	auto[1]	auto[1]	auto[0]	79178	1			T1	59		T2	1		T3	251
fifo_depth[12]	auto[1]	auto[1]	auto[1]	74344	1			T1	12		T2	3		T8	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	28427	1			T3	5		T5	118		T10	10
fifo_depth[13]	auto[0]	auto[0]	auto[1]	28085	1			T3	248		T5	612		T10	11
fifo_depth[13]	auto[0]	auto[1]	auto[0]	31245	1			T3	76		T5	230		T10	3
fifo_depth[13]	auto[0]	auto[1]	auto[1]	26752	1			T3	145		T5	60		T10	3
fifo_depth[13]	auto[1]	auto[0]	auto[0]	32245	1			T1	16		T3	370		T5	397
fifo_depth[13]	auto[1]	auto[0]	auto[1]	33827	1			T1	9		T2	10		T3	79
fifo_depth[13]	auto[1]	auto[1]	auto[0]	36245	1			T1	30		T2	1		T3	242
fifo_depth[13]	auto[1]	auto[1]	auto[1]	30641	1			T1	7		T2	3		T5	142
fifo_depth[14]	auto[0]	auto[0]	auto[0]	49353	1			T3	66		T8	2		T5	648
fifo_depth[14]	auto[0]	auto[0]	auto[1]	49639	1			T3	528		T5	621		T10	3
fifo_depth[14]	auto[0]	auto[1]	auto[0]	46163	1			T3	147		T8	2		T5	421
fifo_depth[14]	auto[0]	auto[1]	auto[1]	48639	1			T3	153		T5	288		T10	5
fifo_depth[14]	auto[1]	auto[0]	auto[0]	51216	1			T1	8		T3	427		T5	446
fifo_depth[14]	auto[1]	auto[0]	auto[1]	51628	1			T1	6		T2	5		T3	209
fifo_depth[14]	auto[1]	auto[1]	auto[0]	59458	1			T1	10		T3	378		T8	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	49887	1			T1	5		T5	438		T10	4
fifo_depth[15]	auto[0]	auto[0]	auto[0]	28076	1			T3	1		T8	1		T5	612
fifo_depth[15]	auto[0]	auto[0]	auto[1]	27601	1			T3	180		T5	460		T10	3
fifo_depth[15]	auto[0]	auto[1]	auto[0]	24879	1			T3	49		T5	169		T39	380
fifo_depth[15]	auto[0]	auto[1]	auto[1]	27101	1			T3	107		T5	33		T10	1
fifo_depth[15]	auto[1]	auto[0]	auto[0]	29037	1			T1	3		T3	326		T5	317
fifo_depth[15]	auto[1]	auto[0]	auto[1]	27985	1			T1	2		T3	65		T5	394
fifo_depth[15]	auto[1]	auto[1]	auto[0]	32048	1			T1	5		T3	357		T5	405
fifo_depth[15]	auto[1]	auto[1]	auto[1]	26454	1			T5	98		T10	1		T39	115
fifo_depth[16]	auto[0]	auto[0]	auto[0]	115088	1			T3	39		T5	897		T39	3083
fifo_depth[16]	auto[0]	auto[0]	auto[1]	106680	1			T3	375		T8	1		T5	670
fifo_depth[16]	auto[0]	auto[1]	auto[0]	108664	1			T3	514		T8	1		T5	792
fifo_depth[16]	auto[0]	auto[1]	auto[1]	122233	1			T3	1018		T8	1		T5	282
fifo_depth[16]	auto[1]	auto[0]	auto[0]	118639	1			T3	257		T8	1		T5	1590
fifo_depth[16]	auto[1]	auto[0]	auto[1]	112833	1			T2	1		T3	128		T5	371
fifo_depth[16]	auto[1]	auto[1]	auto[0]	125265	1			T3	273		T5	4439		T10	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	115837	1			T2	1		T5	1208		T39	3296